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eZ80Acclaim!TM Flash Microcontrollers
EZ80F92/eZ80F93
Product Specification
PRELIMINARY PS015309-1004
ZiLOG Worldwide Headquarters * 532 Race Street * San Jose, CA 95126 Telephone: 408.558.8500 * Fax: 408.558.8300 * www.ZiLOG.com
This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters
532 Race Street San Jose, CA 95126 Telephone: 408.558.8500 Fax: 408.558.8300 www.zilog.com
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated.
Document Disclaimer
(c) 2004 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
PS015309-1004
PRELIMINARY
EZ80F92/eZ80F93 Product Specification
iii
Revision History
Each instance in Table 1 reflects a change to this document from its previous revision. To see more detail, click the appropriate link in the table.
Table 1. Revision History of this Document; Revision Level Section 09 Page # All 82 229 232 89
Date October. 2004
Description
Formatted to current publication standards Timer Control Register Figure 57 Figure 59 Real-Time Clock Oscillator and Source Selection Clarified RST_EN descriptions. Corrected CS rise time label from T8 to T6. Corrected CS rise time label from T8 to T6. Clarified language describing RTC drive frequency.
PS015309-1004
PRELIMINARY
Revision History
EZ80F92/eZ80F93 Product Specification
iv
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .viii List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 eZ80(R) CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Peripheral Power-Down Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 33 33 34 36 36 36 36 37 40 40 40 43 44
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Chip Selects and Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory and I/O Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WAIT Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 49 49 51 52 52
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PRELIMINARY
Table of Contents
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v
Chip Selects During Bus Request/Bus Acknowledge Cycles . . . . . . . . . . . . . . . . . . Bus Mode Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ80 Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z80 Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IntelTM Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motorola Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Reload Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Reload Timers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Reload Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Reload Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-Time Clock Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-Time Clock Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-Time Clock Oscillator and Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . Real-Time Clock Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-Time Clock Recommended Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Recommended Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BRG Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Infrared Encoder/Decoder Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loopback Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53 54 54 54 56 64 68 73 73 74 75 77 77 78 82 88 88 89 89 89 89 90
104 105 105 106 108 109 110 111 124 124 125 125 127 128 128 128
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PRELIMINARY
Table of Contents
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vi
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transfer Procedure with SPI Configured as the Master . . . . . . . . . . . . . . . . . Data Transfer Procedure with SPI Configured as a Slave . . . . . . . . . . . . . . . . . . . SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Serial I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transferring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZiLOG Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI-Supported Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Clock and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation of the EZ80F92 Device During ZDI Breakpoints . . . . . . . . . . . . . . . . . Bus Requests During ZDI DEBUG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Write Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Read Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to On-Chip Instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCI Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCI Information Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130 131 133 133 134 134 135 135 140 140 142 143 145 152 161 161 162 162 163 164 165 166 167 168 169 170 170 186 186 186 187 188
Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 RAM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Arrangement in the EZ80F92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Arrangement in the eZ80F93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 192 193 193 194
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Table of Contents
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Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Flash Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 eZ80(R) CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Op-Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 20 MHz Primary Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 32 KHz Real-Time Clock Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . 219 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POR and VBO Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Current Consumption Under Various Operating Conditions . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait State Timing for Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait State Timing for Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose I/O Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Acknowledge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External System Clock Driver (PHI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZiLOG Debug Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 221 221 223 223 228 229 230 232 233 234 235 236 237 237 238
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
PS015309-1004
PRELIMINARY
Table of Contents
EZ80F92/eZ80F93 Product Specification
viii
List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. EZ80F92 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 100-Pin LQFP Configuration of the EZ80F92 Device . . . . . . . . . . . . . . . . . . 4 GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Example: Memory Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Wait Input Sampling Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Example: Z80 Bus Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 IntelTM Bus Mode Signal and Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 57 Example: IntelTM Bus Mode Read Timing--Separate Address and Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Example: IntelTM Bus Mode Write Timing--Separate Address and Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Example: IntelTM Bus Mode Read Timing--Multiplexed Address and Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Example: IntelTM Bus Mode Write Timing--Multiplexed Address and Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Motorola Bus Mode Signal and Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 64 Watch-Dog Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 PRT Single Pass Mode Operation Example . . . . . . . . . . . . . . . . . . . . . . . . 79 UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Infrared System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SPI Master Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 SPI Slave Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 I2C Clock and Data Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 START and STOP Conditions In I2C Protocol . . . . . . . . . . . . . . . . . . . . . 141 I2C Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Clock Synchronization In I2C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Typical ZDI Debug Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Schematic For Building a Target Board ZPAK II Connector . . . . . . . . . . 162 ZDI Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 ZDI Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 ZDI Address Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 EZ80F92 On-Chip RAM Memory Addressing Example . . . . . . . . . . . . . . 189 eZ80F93 On-Chip RAM Memory Addressing Example . . . . . . . . . . . . . . 190
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PRELIMINARY
List of Figures
EZ80F92/eZ80F93 Product Specification
ix
Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
Recommended Crystal Oscillator Configuration (20MHz operation) . . . . Recommended Crystal Oscillator Configuration (32KHz operation) . . . . ICC Versus WAIT States as a Function of Frequency . . . . . . . . . . . . . . . . ICC Versus Frequency as a Function of WAIT States . . . . . . . . . . . . . . . . ICC Versus Temperature as a Function of Frequency . . . . . . . . . . . . . . . . ICC Versus Frequency in HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . ICC Versus Temperature in SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait State Timing for Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait State Timing for Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
218 219 224 225 226 227 228 230 232 233 234 235 236
PS015309-1004
PRELIMINARY
List of Figures
EZ80F92/eZ80F93 Product Specification
x
List of Tables
Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Revision History of this Document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii 100-Pin LQFP Pin Identification of the EZ80F92 Device . . . . . . . . . . . . . . . 5 Pin Characteristics of the EZ80F92 Device . . . . . . . . . . . . . . . . . . . . . . . . . 20 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Clock Peripheral Power-Down Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Clock Peripheral Power-Down Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 39 GPIO Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Port x Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Port x Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Port x Alternate Registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Port x Alternate Registers 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Interrupt Vector Sources by Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Vectored Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Register Values for Memory Chip Select Example in Figure 6 . . . . . . . . . 51 Z80 Bus Mode Read States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Z80 Bus Mode Write States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 IntelTM Bus Mode Read States (Separate Address and Data Buses) . . . . . . . 57 IntelTM Bus Mode Write States (Separate Address and Data Buses) . . . . . . 58 IntelTM Bus Mode Read States (Multiplexed Address and Data Bus). . . . . . 61 IntelTM Bus Mode Write States (Multiplexed Address and Data Bus) . . . . . 61 Motorola Bus Mode Read States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Motorola Bus Mode Write States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Chip Select x Lower Bound Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Chip Select x Upper Bound Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Chip Select x Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Chip Select x Bus Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Watch-Dog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . . . . . 74 Watch-Dog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Watch-Dog Timer Reset Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 PRT Single Pass Mode Operation Example . . . . . . . . . . . . . . . . . . . . . . . . . 79 PRT Continuous Mode Operation Example . . . . . . . . . . . . . . . . . . . . . . . . 80 PRT Continuous Mode Operation Example . . . . . . . . . . . . . . . . . . . . . . . . . 80 PRT Timer Out Operation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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PRELIMINARY
List of Tables
EZ80F92/eZ80F93 Product Specification
xi
Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70.
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Timer Data Register--Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Timer Data Register--High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Timer Reload Register--Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Timer Reload Register--High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Timer Input Source Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Real-Time Clock Seconds Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Real-Time Clock Minutes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Real-Time Clock Hours Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Real-Time Clock Day-of-the-Week Register . . . . . . . . . . . . . . . . . . . . . . . . 93 Real-Time Clock Day-of-the-Month Register . . . . . . . . . . . . . . . . . . . . . . . 94 Real-Time Clock Month Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Real-Time Clock Year Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Real-Time Clock Century Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Real-Time Clock Alarm Seconds Register . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Real-Time Clock Alarm Minutes Register . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Real-Time Clock Alarm Hours Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Real-Time Clock Alarm Day-of-the-Week Register . . . . . . . . . . . . . . . . . 101 Real-Time Clock Alarm Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 102 Real-Time Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 UART Baud Rate Generator Register--Low Bytes . . . . . . . . . . . . . . . . . . 110 UART Baud Rate Generator Register--High Bytes . . . . . . . . . . . . . . . . . 111 UART Receive Buffer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 UART Transmit Holding Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 UART Interrupt Enable Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 UART Interrupt Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 114 UART Interrupt Status Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 UART FIFO Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 UART Line Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 UART Character Parameter Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Parity Select Definition for Multidrop Communications . . . . . . . . . . . . . . 118 UART Modem Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 UART Line Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 UART Modem Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 UART Scratch Pad Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 IrDA Physical Layer 1.4 Pulse Durations Specifications . . . . . . . . . . . . . . 126
PS015309-1004
PRELIMINARY
List of Tables
EZ80F92/eZ80F93 Product Specification
xii
Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106.
Frequency Divider Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Mode Selection when using the IrDA Encoder/Decoder . . . . . . . . Infrared Encoder/Decoder Control Registers . . . . . . . . . . . . . . . . . . . . . . . SPI Clock Phase and Clock Polarity Operation . . . . . . . . . . . . . . . . . . . . . SPI Baud Rate Generator Register--Low Byte . . . . . . . . . . . . . . . . . . . . . SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Baud Rate Generator Register--High Byte (SPI_BRG_H = 00B9h) . SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Transmit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Receive Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Master Transmit Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Master Transmit Status Codes For Data Bytes . . . . . . . . . . . . . . . . . . I2C 10-Bit Master Transmit Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . I2C Master Receive Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Master Receive Status Codes For Data Bytes . . . . . . . . . . . . . . . . . . . I2C Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Slave Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Extended Slave Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Clock Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended ZDI Clock vs. System Clock Frequency . . . . . . . . . . . . . . ZDI Write Only Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Read Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Address Match Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI BREAK Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Master Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Write Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Read/Write Control Register Functions . . . . . . . . . . . . . . . . . . . . . . . ZDI Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Store 4:0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Write Memory Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ80 Product ID Low Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
127 128 129 132 135 137 137 138 139 139 146 147 147 148 150 152 153 154 154 156 157 157 159 160 162 169 170 171 172 174 175 176 178 179 180 181
PS015309-1004
PRELIMINARY
List of Tables
EZ80F92/eZ80F93 Product Specification
xiii
Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142.
eZ80 Product ID High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ80 Product ID Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Read Register Low, High and Upper . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Read Memory Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM Address Upper Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Key Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Address Upper Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Frequency Divider Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Frequency Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Write/Erase Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Row Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Column Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Program Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Transfer and Compare Instructions . . . . . . . . . . . . . . . . . . . . . . . . . Exchange Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rotate and Shift Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Op Code Map--First Op Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Op Code Map--Second Op Code after 0CBh . . . . . . . . . . . . . . . . . . . . . . Op Code Map--Second Op Code After 0DDh . . . . . . . . . . . . . . . . . . . . . Op Code Map--Second Op Code After 0EDh . . . . . . . . . . . . . . . . . . . . . Op Code Map--Second Op Code After 0FDh . . . . . . . . . . . . . . . . . . . . .
181 182 182 183 184 185 187 191 191 197 198 198 199 200 200 201 203 204 204 205 206 207 207 207 208 208 209 209 209 210 210 211 212 213 214 215
PS015309-1004
PRELIMINARY
List of Tables
EZ80F92/eZ80F93 Product Specification
xiv
Table 143. Table 144. Table 145. Table 146. Table 147. Table 148. Table 149. Table 150. Table 151. Table 152. Table 153. Table 154. Table 155. Table 156. Table 157. Table 158. Table 159.
Op Code Map--Fourth Byte After 0DDh, 0CBh, and dd . . . . . . . . . . . . . Op Code Map--Fourth Byte After 0FDh, 0CBh, and dd . . . . . . . . . . . . . Recommended Crystal Oscillator Specifications. . . . . . . . . . . . . . . . . . . . Recommended Crystal Oscillator Specifications. . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POR and VBO Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External I/O Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Port Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Acknowledge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHI System Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
216 217 219 220 221 222 223 229 230 231 232 233 236 237 237 238 240
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List of Tables
EZ80F92/eZ80F93 Product Specification
1
Architectural Overview
The EZ80F92 device is a high-speed single-cycle instruction-fetch microcontroller with a maximum clock speed of 20 MHz. It is the first member of ZiLOG's new eZ80Acclaim!TM product family, which offers on-chip Flash program memory. The EZ80F92 device can operate in Z80-compatible addressing mode (64 KB) or full 24-bit addressing mode (16 MB). The rich peripheral set of the EZ80F92 device makes it suitable for a variety of applications including industrial control, embedded communication, and point-of-sale terminals. Note: Additionally, ZiLOG offers the eZ80F93 device, which features scaled-down memory options. For purposes of clarity, this document refers to both devices collectively as the EZ80F92 device, unless otherwise specified.
Features
* * * * * * * * * * * * * *
Single-cycle instruction fetch, high-performance, pipelined eZ80(R) CPU core1 EZ80F92 contains 128 KB Flash memory and 8 KB SRAM eZ80F93 contains 64 KB Flash memory and 4 KB SRAM Low power features including SLEEP mode, HALT mode, and selective peripheral power-down control Two UARTs with independent baud rate generators SPI with independent clock rate generator I2C with independent clock rate generator IrDA-compliant infrared encoder/decoder New DMA-like CPU instructions for efficient block data transfer Glueless external peripheral interface with 4 Chip Selects, individual Wait State generators, and an external WAIT input pin--supports Z80-, Intel-, and Motorola-style buses Fixed-priority vectored interrupts (both internal and external) and interrupt controller Real-Time Clock with on-chip 32 KHz oscillator, selectable 50/60 Hz input, and separate VDD pin for battery backup Six 16-bit Counter/Timers with clock dividers and direct input/output drive Watch-Dog Timer
1. For simplicity, the term eZ80(R) CPU is referred to as CPU for the bulk of this document.
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Architectural Overview
EZ80F92/eZ80F93 Product Specification
2
* * * *
24 bits of General-Purpose I/O and ZDI debug interfaces 100-pin LQFP package 3.0-3.6 V supply voltage with 5 V tolerant inputs Operating Temperature Range: - Standard: 0C to +70C - Extended: -40C to +105C
Note: All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for which BYTE is active Low. Power connections follow these conventional descriptions:
Connection Power Ground Circuit VCC GND Device VDD VSS
Block Diagram
Figure 1 illustrates a block diagram of the EZ80F92 processor.
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Architectural Overview
EZ80F92/eZ80F93 Product Specification
3
Real-Time Clock and 32KHz Oscillator
RTC_VDD RTC_XIN RTC_XOUT
SCL SDA
I2C Serial Interface Bus Controller DATA[7:0]
BUSACK BUSREQ INSTRD IORQ MREQ RD WR
SCK SS MISO MOSI
SPI Serial Parallel Interface
eZ80(R) CPU
NMI RESET HALT_SLP
ADDR[23:0]
128KB/64KB Flash Memory
JTAG/ZDI Debug Interface
JTAG / ZDI Signals (5)
CTS0/1 DCD0/1 DSR0/1 DTR0/1 RI0/1 RTS0/1 RXD0/1 TXD0/1 UART Universal Asynchronous Receiver/ Transmitter (2)
WAIT 8KB/4KB SRAM Interrupt Vector [7:0] Interrupt Controller Chip Select & Wait State Generator CS0 CS1 CS2 CS3 DATA[7:0] ADDR[23:0] WDT Watchdog Timer
IrDA Encoder/ Decoder
GPIO 8-bit General Purpose I/O Port (3)
Crystal Oscillator and System Clock Generator
Programmable Reload Timer/Counter (6)
Figure 1.EZ80F92 Block Diagram
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PRELIMINARY
T4_OUT T5_OUT
IR_TxD
PB[7:0]
PC[7:0]
IR_RxD
PD[7:0]
T0_IN T1_IN T2_IN T3_IN
XIN XOUT PHI
Architectural Overview
EZ80F92/eZ80F93 Product Specification
4
Pin Description
Figure 2 illustrates the pin layout of the EZ80F92 device in the 100-pin LQFP package. Table 2 describes the pins and their functions.
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PHI SCL SDA VSS VDD PB7/MOSI PB6/MISO PB5/T5_OUT PB4/T4_OUT PB3/SCK PB2/SS PB1/T1_IN PB0/T0_IN VDD XOUT XIN VSS PC7/RI1 PC6/DCD1 PC5/DSR1 PC4/DTR1 PC3/CTS1 PC2//RTS1 PC1/RxD1 PC0/TxD1 PS015309-1004 ADDR21 ADDR22 ADDR23 CS0 CS1 CS2 CS3 VDD VSS DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 VDD VSS IORQ MREQ RD WR INSTRD WAIT 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PRELIMINARY ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 VDD VSS ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 VDD VSS ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100-Pin LQFP
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PD7/RI0 PD6/DCD0 PD5/DSR0 PD4/DTR0 PD3/CTS0 PD2/RTS0 PD1/RxD0/IR_RxD PD0/TxD0/IR_TxD VDD TDO TDI TRIGOUT TCK TMS VSS RTC_VDD RTC_XOUT RTC_XIN VSS VDD HALT_SLP BUSACK BUSREQ NMI RESET
Figure 2.100-Pin LQFP Configuration of the EZ80F92 Device
Architectural Overview
EZ80F92/eZ80F93 Product Specification
5
Table 2. 100-Pin LQFP Pin Identification of the EZ80F92 Device Pin # 1 Symbol ADDR0 Function Address Bus Signal Direction Bidirectional Description Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects.
2
ADDR1
Address Bus
Bidirectional
3
ADDR2
Address Bus
Bidirectional
4
ADDR3
Address Bus
Bidirectional
5
ADDR4
Address Bus
Bidirectional
6
ADDR5
Address Bus
Bidirectional
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Architectural Overview
EZ80F92/eZ80F93 Product Specification
6
Table 2. 100-Pin LQFP Pin Identification of the EZ80F92 Device (Continued) Pin # 7 8 9 Symbol VDD VSS ADDR6 Function Power Supply Ground Address Bus Bidirectional Signal Direction Description Power Supply. Ground. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects.
10
ADDR7
Address Bus
Bidirectional
11
ADDR8
Address Bus
Bidirectional
12
ADDR9
Address Bus
Bidirectional
13
ADDR10
Address Bus
Bidirectional
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EZ80F92/eZ80F93 Product Specification
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Table 2. 100-Pin LQFP Pin Identification of the EZ80F92 Device (Continued) Pin # 14 Symbol ADDR11 Function Address Bus Signal Direction Bidirectional Description Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Power Supply. Ground. Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects.
15
ADDR12
Address Bus
Bidirectional
16
ADDR13
Address Bus
Bidirectional
17
ADDR14
Address Bus
Bidirectional
18 19 20
VDD VSS ADDR15
Power Supply Ground Address Bus
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Architectural Overview
EZ80F92/eZ80F93 Product Specification
8
Table 2. 100-Pin LQFP Pin Identification of the EZ80F92 Device (Continued) Pin # 21 Symbol ADDR16 Function Address Bus Signal Direction Bidirectional Description Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects.
22
ADDR17
Address Bus
Bidirectional
23
ADDR18
Address Bus
Bidirectional
24
ADDR19
Address Bus
Bidirectional
25
ADDR20
Address Bus
Bidirectional
26
ADDR21
Address Bus
Bidirectional
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EZ80F92/eZ80F93 Product Specification
9
Table 2. 100-Pin LQFP Pin Identification of the EZ80F92 Device (Continued) Pin # 27 Symbol ADDR22 Function Address Bus Signal Direction Bidirectional Description Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I/O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select/Wait State Generator block to generate Chip Selects. CS0 Low indicates that an access is occurring in the defined CS0 memory or I/ O address space. CS1 Low indicates that an access is occurring in the defined CS1 memory or I/ O address space. CS2 Low indicates that an access is occurring in the defined CS2 memory or I/ O address space. CS3 Low indicates that an access is occurring in the defined CS3 memory or I/ O address space. Power Supply. Ground. Bidirectional The data bus transfers data to and from I/O and memory devices. The eZ80Acclaim!TM drives these lines only during Write cycles when the CPU is the bus master. The data bus transfers data to and from I/O and memory devices. The CPU drives these lines only during Write cycles when the CPU is the bus master.
28
ADDR23
Address Bus
Bidirectional
29
CS0
Chip Select 0
Output, Active Low
30
CS1
Chip Select 1
Output, Active Low
31
CS2
Chip Select 2
Output, Active Low
32
CS3
Chip Select 3
Output, Active Low
33 34 35
VDD VSS DATA0
Power Supply Ground Data Bus
36
DATA1
Data Bus
Bidirectional
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Architectural Overview
EZ80F92/eZ80F93 Product Specification
10
Table 2. 100-Pin LQFP Pin Identification of the EZ80F92 Device (Continued) Pin # 37 Symbol DATA2 Function Data Bus Signal Direction Bidirectional Description The data bus transfers data to and from I/O and memory devices. The CPU drives these lines only during Write cycles when the CPU is the bus master. The data bus transfers data to and from I/O and memory devices. The CPU drives these lines only during Write cycles when the CPU is the bus master. The data bus transfers data to and from I/O and memory devices. The CPU drives these lines only during Write cycles when the CPU is the bus master. The data bus transfers data to and from I/O and memory devices. The CPU drives these lines only during Write cycles when the CPU is the bus master. The data bus transfers data to and from I/O and memory devices. The CPU drives these lines only during Write cycles when the CPU is the bus master. The data bus transfers data to and from I/O and memory devices. The CPU drives these lines only during Write cycles when the CPU is the bus master. Power Supply. Ground. Bidirectional, Active Low IORQ indicates that the CPU is accessing a location in I/O space. RD and WR indicate the type of access. It is an input in bus acknowledge cycles. MREQ Low indicates that the CPU is accessing a location in memory. The RD, WR, and INSTRD signals indicate the type of access. It is an input in bus acknowledge cycles. RD Low indicates that the CPU is reading from the current address location. This pin is tristated during bus acknowledge cycles.
38
DATA3
Data Bus
Bidirectional
39
DATA4
Data Bus
Bidirectional
40
DATA5
Data Bus
Bidirectional
41
DATA6
Data Bus
Bidirectional
42
DATA7
Data Bus
Bidirectional
43 44 45
VDD VSS IORQ
Power Supply Ground Input/Output Request
46
MREQ
Memory Request
Bidirectional, Active Low
47
RD
Read
Output, Active Low
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Architectural Overview
EZ80F92/eZ80F93 Product Specification
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Table 2. 100-Pin LQFP Pin Identification of the EZ80F92 Device (Continued) Pin # 48 Symbol WR Function Write Signal Direction Output, Active Low Description WR indicates that the CPU is writing to the current address location. This pin is tristated during bus acknowledge cycles. INSTRD (with MREQ and RD) indicates the CPU is fetching an instruction from memory. This pin is tristated during bus acknowledge cycles. Driving the WAIT pin Low forces the CPU to wait additional clock cycles for an external peripheral or external memory to complete its Read or Write operation.
49
INSTRD
Instruction Output, Active Low Read Indicator
50
WAIT
WAIT Request Input, Active Low
51
RESET
System Reset Schmitt Trigger Input, This signal is used to initialize the CPU. Active Low This input must be Low for a minimum of 3 system clock cycles, and must be held Low until the clock is stable. This input includes a Schmitt trigger to allow RC rise times. Nonmaskable Schmitt Trigger Input, The NMI input is a higher priority input than Interrupt Active Low the maskable interrupts. It is always recognized at the end of an instruction, regardless of the state of the interrupt enable control bits. This input includes a Schmitt trigger to allow RC rise times. Bus Request Input, Active Low External devices can request the CPU to release the memory interface bus for their use, by driving this pin Low. The CPU responds to a Low on BUSREQ, by tristating the address, data, and control signals, and by driving the BUSACK line Low. During bus acknowledge cycles ADDR[23:0], IORQ, and MREQ are inputs. A Low on this pin indicates that the CPU has entered either HALT or SLEEP mode because of execution of either a HALT or SLP instruction. Power Supply. Ground. Input This pin is the input to the low-power 32 KHz crystal oscillator for the Real-Time Clock.
52
NMI
53
BUSREQ
54
BUSACK
Bus Acknowledge
Output, Active Low
55
HALT_SLP
HALT and SLEEP Indicator Power Supply Ground Real-Time Clock Crystal Input
Output, Active Low
56 57 58
VDD VSS RTC_XIN
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EZ80F92/eZ80F93 Product Specification
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Table 2. 100-Pin LQFP Pin Identification of the EZ80F92 Device (Continued) Pin # 59 Symbol Function Signal Direction Bidirectional Description This pin is the output from the low-power 32 KHz crystal oscillator for the Real-Time Clock. This pin is an input when the RTC is configured to operate from 50/60 Hz input clock signals and the 32 KHz crystal oscillator is disabled. Power supply for the Real-Time Clock and associated 32 KHz oscillator. Isolated from the power supply to the remainder of the chip. A battery can be connected to this pin to supply constant power to the Real-Time Clock and 32 KHz oscillator. Ground. Input Input JTAG Mode Select Input. JTAG and ZDI clock input. Active High trigger event indicator. JTAG data input pin. Functions as ZDI data I/O pin when JTAG is disabled. JTAG data output pin. Power Supply. Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. This pin is used by the UART to transmit asynchronous serial data. This signal is multiplexed with PD0. This pin is used by the IrDA encoder/ decoder to transmit serial data. This signal is multiplexed with PD0.
RTC_XOUT Real-Time Clock Crystal Output
60
RTC_VDD
Real-Time Clock Power Supply
61 62 63 64 65 66 67 68
VSS TMS TCK TRIGOUT TDI TDO VDD PD0
Ground JTAG Test Mode Select JTAG Test Clock
JTAG Test Output Trigger Output JTAG Test Data In JTAG Test Data Out Power Supply GPIO Port D Bidirectional Output
TxD0
UART Output Transmit Data IrDA Transmit Output Data
IR_TxD
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Architectural Overview
EZ80F92/eZ80F93 Product Specification
13
Table 2. 100-Pin LQFP Pin Identification of the EZ80F92 Device (Continued) Pin # 69 Symbol PD1 Function GPIO Port D Signal Direction Bidirectional Description This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. This pin is used by the UART to receive asynchronous serial data. This signal is multiplexed with PD1. This pin is used by the IrDA encoder/ decoder to receive serial data. This signal is multiplexed with PD1. This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. Modem control signal from UART. This signal is multiplexed with PD2. This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. Modem status signal to the UART. This signal is multiplexed with PD3.
RxD0
Receive Data
Input
IR_RxD
IrDA Receive Data GPIO Port D
Input
70
PD2
Bidirectional
RTS0 71 PD3
Request To Send GPIO Port D
Output, Active Low Bidirectional
CTS0
Clear To Send Input, Active Low
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EZ80F92/eZ80F93 Product Specification
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Table 2. 100-Pin LQFP Pin Identification of the EZ80F92 Device (Continued) Pin # 72 Symbol PD4 Function GPIO Port D Signal Direction Bidirectional Description This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. Modem control signal to the UART. This signal is multiplexed with PD4. This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. Modem status signal to the UART. This signal is multiplexed with PD5. This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. Modem status signal to the UART. This signal is multiplexed with PD6. This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. Modem status signal to the UART. This signal is multiplexed with PD7.
DTR0 73 PD5
Data Terminal Output, Active Low Ready GPIO Port D Bidirectional
DSR0 74 PD6
Data Set Ready GPIO Port D
Input, Active Low Bidirectional
DCD0 75 PD7
Data Carrier Detect GPIO Port D
Input, Active Low Bidirectional
RI0
Ring Indicator Input, Active Low
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Table 2. 100-Pin LQFP Pin Identification of the EZ80F92 Device (Continued) Pin # 76 Symbol PC0 Function GPIO Port C Signal Direction Bidirectional Description This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. This pin is used by the UART to transmit asynchronous serial data. This signal is multiplexed with PC0. This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. This pin is used by the UART to receive asynchronous serial data. This signal is multiplexed with PC1. This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. Modem control signal from UART. This signal is multiplexed with PC2.
TxD1
Transmit Data Output
77
PC1
GPIO Port C
Bidirectional
RxD1
Receive Data
Input
78
PC2
GPIO Port C
Bidirectional
RTS1
Request To Send
Output, Active Low
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Table 2. 100-Pin LQFP Pin Identification of the EZ80F92 Device (Continued) Pin # 79 Symbol PC3 Function GPIO Port C Signal Direction Bidirectional Description This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. Modem status signal to the UART. This signal is multiplexed with PC3. This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. Modem control signal to the UART. This signal is multiplexed with PC4. This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. Modem status signal to the UART. This signal is multiplexed with PC5. This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. Modem status signal to the UART. This signal is multiplexed with PC6.
CTS1 80 PC4
Clear To Send Input, Active Low GPIO Port C Bidirectional
DTR1 81 PC5
Data Terminal Output, Active Low Ready GPIO Port C Bidirectional
DSR1 82 PC6
Data Set Ready GPIO Port C
Input, Active Low Bidirectional
DCD1
Data Carrier Detect
Input, Active Low
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17
Table 2. 100-Pin LQFP Pin Identification of the EZ80F92 Device (Continued) Pin # 83 Symbol PC7 Function GPIO Port C Signal Direction Bidirectional Description This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. Modem status signal to the UART. This signal is multiplexed with PC7. Ground. This pin is the input to the onboard crystal oscillator for the primary system clock. If an external oscillator is used, its clock output should be connected to this pin. When a crystal is used, it should be connected between XIN and XOUT. This pin is the output of the onboard crystal oscillator. When used, a crystal should be connected between XIN and XOUT. Power Supply. Bidirectional This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. Alternate clock source for Programmable Reload Timers 0 and 2. This signal is multiplexed with PB0.
RI1 84 85 VSS XIN
Ring Indicator Input, Active Low Ground System Clock Input Oscillator Input
86
XOUT
System Clock Output Oscillator Output Power Supply GPIO Port B
87 88
VDD PB0
T0_IN
Timer 0 In
Input
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Table 2. 100-Pin LQFP Pin Identification of the EZ80F92 Device (Continued) Pin # 89 Symbol PB1 Function GPIO Port B Signal Direction Bidirectional Description This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. Alternate clock source for Programmable Reload Timers 1 and 3. This signal is multiplexed with PB1. This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. The slave select input line is used to select a slave device in SPI mode. This signal is multiplexed with PB2. This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. SPI serial clock. This signal is multiplexed with PB3. This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. Programmable Reload Timer 4 timer-out signal. This signal is multiplexed with PB4.
T1_IN
Timer 1 In
Input
90
PB2
GPIO Port B
Bidirectional
SS
Slave Select
Input, Active Low
91
PB3
GPIO Port B
Bidirectional
SCK 92 PB4
SPI Serial Clock GPIO Port B
Bidirectional Bidirectional
T4_OUT
Timer 4 Out
Output
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Table 2. 100-Pin LQFP Pin Identification of the EZ80F92 Device (Continued) Pin # 93 Symbol PB5 Function GPIO Port B Signal Direction Bidirectional Description This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. Programmable Reload Timer 5 timer-out signal. This signal is multiplexed with PB5. This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. The MISO line is configured as an input when the CPU is an SPI master device and as an output when CPU is an SPI slave device. This signal is multiplexed with PB6. This pin can be used for general-purpose I/ O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. The MOSI line is configured as an output when the CPU is an SPI master device and as an input when the CPU is an SPI slave device. This signal is multiplexed with PB7. Power Supply. Ground. This pin carries the I2C data signal. This pin is used to receive and transmit the I2C clock. This pin is an output driven by the internal system clock.
T5_OUT 94 PB6
Timer 5 Out GPIO Port B
Output Bidirectional
MISO
Master In, Slave Out
Bidirectional
95
PB7
GPIO Port B
Bidirectional
MOSI
Master Out, Slave In
Bidirectional
96 97 98 99 100
VDD VSS SDA SCL PHI
Power Supply Ground I2C Serial Data Bidirectional I2C Serial Clock Bidirectional
System Clock Output
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Pin Characteristics
Table 3 describes the characteristics of each pin in the EZ80F92 device's 100-pin LQFP package.
Table 3. Pin Characteristics of the EZ80F92 Device Schmitt Trigger Input No No No No No No
Pin # Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 VDD VSS ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 VDD VSS ADDR15 ADDR16 ADDR17 ADDR18 ADDR19
Reset Direction Direction I/O I/O I/O I/O I/O I/O O O O O O O
Active Low/High N/A N/A N/A N/A N/A N/A
Tristate Pull Output Up/Down Yes Yes Yes Yes Yes Yes No No No No No No
Open Drain/ Source No No No No No No
I/O I/O I/O I/O I/O I/O I/O I/O I/O
O O O O O O O O O
N/A N/A N/A N/A N/A N/A N/A N/A N/A
Yes Yes Yes Yes Yes Yes Yes Yes Yes
No No No No No No No No No
No No No No No No No No No
No No No No No No No No No
I/O I/O I/O I/O I/O
O O O O O
N/A N/A N/A N/A N/A
Yes Yes Yes Yes Yes
No No No No No
No No No No No
No No No No No
Note: I = Input, O = Output, I/O = Input and Output, U = Undefined.
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Table 3. Pin Characteristics of the EZ80F92 Device (Continued) Schmitt Trigger Input No No No No No No No No
Pin # Symbol 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 ADDR20 ADDR21 ADDR22 ADDR23 CS0 CS1 CS2 CS3 VDD VSS DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 VDD VSS IORQ MREQ RD WR INSTRD WAIT RESET
Reset Direction Direction I/O I/O I/O I/O O O O O O O O O O O O O
Active Low/High N/A N/A N/A N/A Low Low Low Low
Tristate Pull Output Up/Down Yes Yes Yes Yes No No No No No No No No No No No No
Open Drain/ Source No No No No No No No No
I/O I/O I/O I/O I/O I/O I/O I/O
I I I I I I I I
N/A N/A N/A N/A N/A N/A N/A N/A
Yes Yes Yes Yes Yes Yes Yes Yes
No No No No No No No No
No No No No No No No No
No No No No No No No No
I/O I/O O O O I I
O O O O O I I
Low Low Low Low Low Low Low
Yes Yes Yes Yes No N/A N/A
No No No No No No No
No No No No No No Yes
No No No No No N/A N/A
Note: I = Input, O = Output, I/O = Input and Output, U = Undefined.
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Table 3. Pin Characteristics of the EZ80F92 Device (Continued) Schmitt Trigger Input Yes No No No
Pin # Symbol 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 NMI BUSREQ BUSACK HALT_SLP VDD VSS RTC_XIN RTC_XOUT RTC_VDD VSS TMS TCK TRIGOUT TDI TDO VDD PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1
Reset Direction Direction I I O O I I O O
Active Low/High Low Low Low Low
Tristate Pull Output Up/Down N/A N/A No No No No No No
Open Drain/ Source N/A N/A No No
I I/O
I U
N/A N/A
N/A N/A
No No
No No
N/A No
I I O I/O O
I I O I U
N/A Rising (In) Falling (Out) High N/A N/A
N/A N/A No Yes Yes
Up Up No No No
No No No No No
N/A N/A No No No
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I I I I I I I I I I
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
No No No No No No No No No No
No No No No No No No No No No
OD & OS OD & OS OD & OS OD & OS OD & OS OD & OS OD & OS OD & OS OD & OS OD & OS
Note: I = Input, O = Output, I/O = Input and Output, U = Undefined.
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Table 3. Pin Characteristics of the EZ80F92 Device (Continued) Schmitt Trigger Input No No No No No No
Pin # Symbol 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PC2 PC3 PC4 PC5 PC6 PC7 VSS XIN XOUT VDD PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VDD VSS SDA SCL PHI
Reset Direction Direction I/O I/O I/O I/O I/O I/O I I I I I I
Active Low/High N/A N/A N/A N/A N/A N/A
Tristate Pull Output Up/Down Yes Yes Yes Yes Yes Yes No No No No No No
Open Drain/ Source OD & OS OD & OS OD & OS OD & OS OD & OS OD & OS
I O
I O
N/A N/A
N/A No
No No
No No
N/A No
I/O I/O I/O I/O I/O I/O I/O I/O
I I I I I I I I
N/A N/A N/A N/A N/A N/A N/A N/A
Yes Yes Yes Yes Yes Yes Yes Yes
No No No No No No No No
No No No No No No No No
OD & OS OD & OS OD & OS OD & OS OD & OS OD & OS OD & OS OD & OS
I/O I/O O
I I O
N/A N/A N/A
Yes Yes Yes
Up Up No
No No No
OD OD No
Note: I = Input, O = Output, I/O = Input and Output, U = Undefined.
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Register Map
All on-chip peripheral registers are accessed in the I/O address space. All I/O operations employ 16-bit addresses. The upper byte of the 24-bit address bus is undefined during all I/O operations (ADDR[23:16] = UU). All I/O operations using 16-bit addresses within the range 0080h-00FFh are routed to the on-chip peripherals. External I/O Chip Selects are not generated if the address space programmed for the I/O Chip Selects overlaps the 0080h-00FFh address range. Registers at unused addresses within the 0080h-00FFh range assigned to on-chip peripherals are not implemented. Read access to such addresses returns unpredictable values and Write access produces no effect. Table 4 diagrams the register map for the EZ80F92 device.
Table 4. Register Map Address (hex) Mnemonic Reset (hex) CPU Page Access #
Name
Programmable Reload Counter/Timers 0080 0081 TMR0_CTL TMR0_DR_L TMR0_RR_L 0082 TMR0_DR_H TMR0_RR_H 0083 0084 TMR1_CTL TMR1_DR_L TMR1_RR_L 0085 TMR1_DR_H TMR1_RR_H 0086 TMR2_CTL Timer 0 Control Register Timer 0 Data Register--Low Byte Timer 0 Reload Register--Low Byte Timer 0 Data Register--High Byte Timer 0 Reload Register--High Byte Timer 1 Control Register Timer 1 Data Register--Low Byte Timer 1 Reload Register--Low Byte Timer 1 Data Register--High Byte Timer 1 Reload Register--High Byte Timer 2 Control Register 00 00 00 00 00 00 00 00 00 00 00 R/W R W R W R/W R W R W R/W 83 84 85 85 86 83 84 85 85 86 83
Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked. 4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b. 5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.
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Table 4. Register Map (Continued) Address (hex) Mnemonic Reset (hex) CPU Page Access #
Name
Programmable Reload Counter/Timers (continued) 0087 TMR2_DR_L TMR2_RR_L 0088 TMR2_DR_H TMR2_RR_H 0089 008A TMR3_CTL TMR3_DR_L TMR3_RR_L 008B TMR3_DR_H TMR3_RR_H 008C 008D TMR4_CTL TMR4_DR_L TMR4_RR_L 008E TMR4_DR_H TMR4_RR_H 008F 0090 TMR5_CTL TMR5_DR_L TMR5_RR_L 0091 TMR5_DR_H TMR5_RR_H 0092 TMR_ISS Timer 2 Data Register--Low Byte Timer 2 Reload Register--Low Byte Timer 2 Data Register--High Byte Timer 2 Reload Register--High Byte Timer 3 Control Register Timer 3 Data Register--Low Byte Timer 3 Reload Register--Low Byte Timer 3 Data Register--High Byte Timer 3 Reload Register--High Byte Timer 4 Control Register Timer 4 Data Register--Low Byte Timer 4 Reload Register--Low Byte Timer 4 Data Register--High Byte Timer 4 Reload Register--High Byte Timer 5 Control Register Timer 5 Data Register--Low Byte Timer 5 Reload Register--Low Byte Timer 5 Data Register--High Byte Timer 5 Reload Register--High Byte Timer Input Source Select Register 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R W R W R/W R W R W R/W R W R W R/W R W R W R/W 84 85 85 86 83 84 85 85 86 83 84 85 85 86 83 84 85 85 86 87
Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked. 4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b. 5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.
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Table 4. Register Map (Continued) Address (hex) Mnemonic Watch-Dog Timer 0093 0094 WDT_CTL WDT_RR Watch-Dog Timer Control Register1 Watch-Dog Timer Reset Register 00/20 XX R/W W 75 76 Reset (hex) CPU Page Access #
Name
General-Purpose Input/Output Ports 009A 009B 009C 009D 009E 009F 00A0 00A1 00A2 00A3 00A4 00A5 PB_DR PB_DDR PB_ALT1 PB_ALT2 PC_DR PC_DDR PC_ALT1 PC_ALT2 PD_DR PD_DDR PD_ALT1 PD_ALT2 Port B Data Register2 Port B Data Direction Register Port B Alternate Register 1 Port B Alternate Register 2 Port C Data Register2 Port C Data Direction Register Port C Alternate Register 1 Port C Alternate Register 2 Port D Data Register2 Port D Data Direction Register Port D Alternate Register 1 Port D Alternate Register 2 XX FF 00 00 XX FF 00 00 XX FF 00 00 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 44 45 45 45 44 45 45 45 44 45 45 45
Chip Select/Wait State Generator 00A8 00A9 00AA 00AB 00AC 00AD CS0_LBR CS0_UBR CS0_CTL CS1_LBR CS1_UBR CS1_CTL Chip Select 0 Lower Bound Register Chip Select 0 Upper Bound Register Chip Select 0 Control Register Chip Select 1 Lower Bound Register Chip Select 1 Upper Bound Register Chip Select 1 Control Register 00 FF E8 00 00 00 R/W R/W R/W R/W R/W R/W 68 69 70 68 69 70
Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked. 4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b. 5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.
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Table 4. Register Map (Continued) Address (hex) Mnemonic Reset (hex) CPU Page Access #
Name
Chip Select/Wait State Generator (continued) 00AE 00AF 00B0 00B1 00B2 00B3 CS2_LBR CS2_UBR CS2_CTL CS3_LBR CS3_UBR CS3_CTL Chip Select 2 Lower Bound Register Chip Select 2 Upper Bound Register Chip Select 2 Control Register Chip Select 3 Lower Bound Register Chip Select 3 Upper Bound Register Chip Select 3 Control Register 00 00 00 00 00 00 R/W R/W R/W R/W R/W R/W 68 69 70 68 69 70
On-Chip RAM Control 00B4 00B5 RAM_CTL RAM_ADDR_U RAM Control Register RAM Address Upper Byte Register 80 FF R/W R/W 191 191
Serial Peripheral Interface (SPI) Block 00B8 00B9 00BA 00BB 00BC SPI_BRG_L SPI_BRG_H SPI_CTL SPI_SR SPI_TSR SPI_RBR SPI Baud Rate Generator Register--Low Byte SPI Baud Rate Generator Register--High Byte SPI Control Register SPI Status Register SPI Transmit Shift Register SPI Receive Buffer Register 02 00 04 00 XX XX R/W R/W R/W R W R 135 137 137 138 139 139
Infrared Encoder/Decoder Block 00BF IR_CTL Infrared Encoder/Decoder Control 00 R/W 129
Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked. 4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b. 5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.
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Table 4. Register Map (Continued) Address (hex) Mnemonic Reset (hex) CPU Page Access #
Name
Universal Asynchronous Receiver/Transmitter 0 (UART0) Block 00C0 UART0_RBR UART0_THR UART0_BRG_L 00C1 UART0_IER UART0_BRG_H 00C2 UART0_IIR UART0_FCTL 00C3 00C4 00C5 00C6 00C7 I2C Block 00C8 00C9 00CA 00CB 00CC I2C_SAR I2C_XSAR I2C_DR I2C_CTL I2C_SR I2C_CCR 00CD I2C_SRR I2C Slave Address Register I2C Extended Slave Address Register I2C Data Register I2C Control Register I2C Status Register I2C Clock Control Register I2C Software Reset Register 00 00 00 00 F8 00 XX R/W R/W R/W R/W R W W 153 154 154 156 157 159 160 UART0_LCTL UART0_MCTL UART0_LSR UART0_MSR UART0_SPR UART 0 Receive Buffer Register UART 0 Transmit Holding Register UART 0 Baud Rate Generator Register-- Low Byte UART 0 Interrupt Enable Register UART 0 Baud Rate Generator Register-- High Byte UART 0 Interrupt Identification Register UART 0 FIFO Control Register UART 0 Line Control Register UART 0 Modem Control Register UART 0 Line Status Register UART 0 Modem Status Register UART 0 Scratch Pad Register XX XX 02 00 00 01 00 00 00 60 XX 00 R W R/W R/W R/W R W R/W R/W R R R/W 112 112 110 113 111 114 115 116 119 120 122 123
Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked. 4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b. 5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.
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Table 4. Register Map (Continued) Address (hex) Mnemonic Reset (hex) CPU Page Access #
Name
Universal Asynchronous Receiver/Transmitter 1 (UART1) Block 00D0 UART1_RBR UART1_THR UART1_BRG_L 00D1 UART1_IER UART1_BRG_H 00D2 UART1_IIR UART1_FCTL 00D3 00D4 00D5 00D6 00D7 UART1_LCTL UART1_MCTL UART1_LSR UART1_MSR UART1_SPR UART 1 Receive Buffer Register UART 1 Transmit Holding Register UART 1 Baud Rate Generator Register-- Low Byte UART 1 Interrupt Enable Register UART 1 Baud Rate Generator Register-- High Byte UART 1 Interrupt Identification Register UART 1 FIFO Control Register UART 1 Line Control Register UART 1 Modem Control Register UART 1 Line Status Register UART 1 Modem Status Register UART 1 Scratch Pad Register XX XX 02 00 00 01 00 00 00 60 XX 00 R W R/W R/W R/W R W R/W R/W R/W R/W R/W 112 112 110 113 111 114 115 116 119 120 122 123
Low-Power Control 00DB 00DC CLK_PPD1 CLK_PPD2 Clock Peripheral Power-Down Register 1 Clock Peripheral Power-Down Register 2 00 00 R/W R/W 38 39
Real-Time Clock 00E0 00E1 00E2 00E3 RTC_SEC RTC_MIN RTC_HRS RTC_DOW RTC Seconds Register3 RTC Minutes Register3 Register3 RTC Hours Register3 RTC Day-of-the-Week XX XX XX 0X R/W R/W R/W R/W 90 91 92 93
Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked. 4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b. 5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.
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Table 4. Register Map (Continued) Address (hex) Mnemonic Real-Time Clock (continued) 00E4 00E5 00E6 00E7 00E8 00E9 00EA 00EB 00EC 00ED RTC_DOM RTC_MON RTC_YR RTC_CEN RTC_ASEC RTC_AMIN RTC_AHRS RTC_ADOW RTC_ACTRL RTC_CTRL RTC Day-of-the-Month Register3 RTC Month Register3 Register3 RTC Year Register3 RTC Century XX XX XX XX XX XX XX 0X 00 x0xxx000b/ x0xxxx10b R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 94 95 96 97 98 99 100 101 102 103 Reset (hex) CPU Page Access #
Name
RTC Alarm Seconds Register RTC Alarm Minutes Register RTC Alarm Hours Register RTC Alarm Day-of-the-Week Register RTC Alarm Control Register RTC Control Register4
Chip Select Bus Mode Control 00F0 00F1 00F2 00F3 CS0_BMC CS1_BMC CS2_BMC CS3_BMC Chip Select 0 Bus Mode Control Register Chip Select 1 Bus Mode Control Register Chip Select 2 Bus Mode Control Register Chip Select 3 Bus Mode Control Register 02 02 02 02 R/W R/W R/W R/W 71 71 71 71
Flash Memory Control Registers 00F5 00F6 00F7 00F8 00F9 00FA FLASH_KEY FLASH_DATA Flash Key Register Flash Data Register 00 XX 0 88 01 FF Register5 W R/W R/W R/W R/W R/W 197 198 198 199 200 201
FLASH_ADDR_U Flash Address Upper Byte Register FLASH_CTRL FLASH_FDIV FLASH_PROT Flash Control Register Flash Frequency Divider Register5 Flash Write/Erase Protection
Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked. 4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b. 5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.
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Table 4. Register Map (Continued) Address (hex) Mnemonic Reset (hex) CPU Page Access #
Name
Flash Memory Control Registers (continued) 00FB 00FC 00FD 00FE 00FF FLASH_IRQ FLASH_PAGE FLASH_ROW FLASH_COL FLASH_PGCTL Flash Interrupt Control Register Flash Page Select Register Flash Row Select Register Flash Column Select Register Flash Program Control Register 00 00 00 00 00 R/W R/W R/W R/W R/W 203 204 204 205 206
Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked. 4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b. 5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.
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eZ80(R) CPU Core
The eZ80(R) is the first 8-bit CPU to support 16 MB linear addressing. Each software module or task under a real-time executive or operating system can operate in Z80-compatible (64 KB) mode or full 24-bit (16 MB) address mode. The CPU instruction set is a superset of the instruction sets for the Z80 and Z180 CPUs. Z80 and Z180 programs can be executed on an eZ80(R) CPU with little or no modification.
Features
* * * * * * * *
Code-compatible with Z80 and Z180 products 24-bit linear address space Single-cycle instruction fetch Pipelined fetch, decode, and execute Dual Stack Pointers for ADL (24-bit) and Z80 (16-bit) memory modes 24-bit CPU registers and ALU (Arithmetic Logic Unit) Debug support Nonmaskable Interrupt (NMI), plus support for 128 maskable vectored interrupts
For more information about the eZ80(R) CPU and its instruction set, please refer to the eZ80 CPU User Manual (UM0077).
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Reset
Reset Operation
The Reset controller within the EZ80F92 device provides a consistent reset function for all types of resets that can affect the system. A system reset, referred to in this document as RESET, returns the EZ80F92 device to a defined state. All internal registers affected by RESET return to their default conditions. RESET configures the GPIO port pins as inputs and clears the CPU's Program Counter to 000000h. Program code execution ceases during RESET. The events that can cause a RESET are:
* * * * * *
Power-On Reset (POR) Low-Voltage Brown-Out (VBO) External RESET pin assertion Watch-Dog Timer (WDT) time-out when configured to generate a RESET Real-Time Clock alarm with the CPU in low-power SLEEP mode Execution of a debug reset command
During a RESET, an internal RESET mode timer holds the system in RESET mode for 257 system clock (SCLK) cycles. The RESET mode timer begins incrementing on the next rising edge of SCLK following deactivation of all RESET events. Note: The user must determine if 257 SCLK cycles provides sufficient time for the primary crystal oscillator to stabilize.
Power-On Reset
A Power-On Reset (POR) occurs each time the supply voltage to the part rises from below the voltage brown-out threshold to above the POR voltage threshold (VPOR). The internal bandgap-referenced voltage detector sends a continuous RESET signal to the Reset controller until the supply voltage (VCC) exceeds the POR voltage threshold. After VCC rises above VPOR, an on-chip analog delay element briefly maintains the RESET signal to the Reset controller (TANA). After this analog delay, the EZ80F92 device is in RESET mode until the RESET mode timer expires. POR operation is illustrated in Figure 3. The signals in this figure are not drawn to scale and are for illustration purposes only.
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VPOR VVBO VCC = 0.0V
VCC = 3.3V
Program Execution
System Clock
Oscillator Startup Internal RESET Signal T ANA RESET mode timer delay
Figure 3.Power-On Reset Operation
Voltage Brown-Out Reset
If, after program execution begins, the supply voltage (VCC) drops below the Voltage Brown-Out threshold (VVBO), the EZ80F92 device resets. The VBO protection circuitry detects the low supply voltage and initiates the RESET via the Reset controller. The EZ80F92 device remains in RESET mode until the supply voltage again returns above the POR voltage threshold (VPOR) and the Reset controller releases the internal RESET signal. The VBO circuitry rejects very short negative brown-out pulses to prevent spurious RESET events. VBO operation is illustrated in Figure 4. The signals in this figure are not drawn to scale and are for illustration purposes only.
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VCC = 3.3V VPOR VVBO Program Execution Voltage Brown-out
VCC = 3.3V
Program Execution
System Clock
Internal RESET Signal RESET mode timer delay
TANA
Figure 4.Voltage Brown-Out Reset Operation
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Low-Power Modes
Overview
The EZ80F92 device provides a range of power-saving features. The highest level of power reduction is provided by SLEEP mode. The next level of power reduction is provided by the HALT instruction. The lowest level of power reduction is provided by the clock peripheral power-down registers.
SLEEP Mode
Execution of the CPU's SLEEP instruction (SLP) places the EZ80F92 device into SLEEP mode. In SLEEP mode, the operating characteristics are:
* * * * *
The primary crystal oscillator is disabled The system clock is disabled The CPU is idle The Program Counter (PC) stops incrementing The 32 KHz crystal oscillator continues to operate and drive the Real-Time Clock and the Watch-Dog Timer (if WDT is configured to operate from the 32 KHz oscillator)
The CPU can be brought out of SLEEP mode by any of the following operations:
* * *
A RESET via the external RESET pin driven Low A RESET via a Real-Time Clock alarm A RESET via execution of a Debug Reset command
After exiting SLEEP mode, the standard RESET delay occurs to allow the primary crystal oscillator to stabilize. Refer to the Reset section on page 33 for more information. Caution: During SLEEP mode, the CPU freezes the last address and drives the address bus with this value. The GPIO ports remain as configured by the user. Prior to entering SLEEP mode, the data bus is driven Low and the control signals MREQ, CS3:0, INSTRD, BUSACK, IOREQ,RD, and WR are driven High.
HALT Mode
Execution of the CPU's HALT instruction places the EZ80F92 device into HALT mode. In HALT mode, the operating characteristics are:
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* * * * * * * * *
Primary crystal oscillator is enabled and continues to operate The system clock is enabled and continues to operate The CPU is idle The Program Counter (PC) stops incrementing
The CPU can be brought out of HALT mode by any of the following operations: A nonmaskable interrupt (NMI) A maskable interrupt A RESET via the external RESET pin driven Low A Watch-Dog Timer time-out (if configured to generate either an NMI or RESET upon time-out) A RESET via execution of a Debug RESET command
To minimize current in HALT mode, the system clock should be disabled for all unused on-chip peripherals via the Clock Peripheral Power-Down Registers. Caution: During HALT mode, the CPU freezes the last address and drives the address bus with this value. The GPIO Ports remain as configured by the user. Prior to entering HALT mode, the data bus is driven Low and the control signals MREQ, CS3:0, INSTRD, BUSACK, IOREQ, RD, and WR are driven High.
Clock Peripheral Power-Down Registers
To reduce power, the Clock Peripheral Power-Down Registers allow the system clock to be disabled unused on-chip peripherals. Upon RESET, all peripherals are enabled. The clock to unused peripherals can be disabled by setting the appropriate bit in the Clock Peripheral Power-Down Registers to 1. When powered down, the peripherals are completely disabled. To reenable, the bit in the Clock Peripheral Power-Down Registers must be cleared to 0. Many peripherals feature separate enable/disable control bits that must be appropriately set for operation. These peripheral specific enable/disable bits do not provide the same level of power reduction as the Clock Peripheral Power-Down Registers. When powered down, the standard peripheral control registers are not accessible for Read or Write access. See Tables 5 and 6.
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Table 5. Clock Peripheral Power-Down Register (CLK_PPD1 = 00DBh) Bit Reset CPU Access 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Note: R/W = Read/Write; R = Read Only.
Bit Position 7 GPIO_D_OFF
Value Description 1 0 System clock to GPIO Port D is powered down. Port D alternate functions do not operate correctly. System clock to GPIO Port D is powered up. System clock to GPIO Port C is powered down. Port C alternate functions do not operate correctly. System clock to GPIO Port C is powered up. System clock to GPIO Port B is powered down. Port B alternate functions do not operate correctly. System clock to GPIO Port B is powered up. Reserved. 1 0 1 0 1 0 1 0 System clock to SPI is powered down. System clock to SPI is powered up. System clock to I2C is powered down. System clock to I2C is powered up. System clock to UART1 is powered down. System clock to UART1 is powered up. System clock to UART0 and IrDA endec is powered down. System clock to UART0 and IrDA endec is powered up.
6 GPIO_C_OFF
1 0
5 GPIO_B_OFF
1 0
4 3 SPI_OFF 2 I2C_OFF 1 UART1_OFF 0 UART0_OFF
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Table 6. Clock Peripheral Power-Down Register 2 (CLK_PPD2 = 00DCh) Bit Reset CPU Access 7 0 R/W 6 0 R 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Note: R/W = Read/Write; R = Read Only.
Bit Position 7 PHI_OFF 6 5 PRT5_OFF 4 PRT4_OFF 3 PRT3_OFF 2 PRT2_OFF 1 PRT1_OFF 0 PRT0_OFF
Value Description 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 PHI Clock output is disabled (output is high-impedance). PHI Clock output is enabled. Reserved. System clock to PRT5 is powered down. System clock to PRT5 is powered up. System clock to PRT4 is powered down. System clock to PRT4 is powered up. System clock to PRT3 is powered down. System clock to PRT3 is powered up. System clock to PRT2 is powered down. System clock to PRT2 is powered up. System clock to PRT1 is powered down. System clock to PRT1 is powered up. System clock to PRT0 is powered down. System clock to PRT0 is powered up.
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General-Purpose Input/Output
GPIO Overview
The EZ80F92 device features 24 General-Purpose Input/Output (GPIO) pins. The GPIO pins are assembled as three 8-bit ports-- Port B, Port C, and Port D. All port signals can be configured for use as either inputs or outputs. In addition, all of the port pins can be used as vectored interrupt sources for the CPU.
GPIO Operation
The GPIO operation is the same for all 3 GPIO ports (Ports B, C, and D). Each port features eight GPIO port pins. The operating mode for each pin is controlled by four bits that are divided between four 8-bit registers. These GPIO mode control registers are:
* * * *
Port x Data Register (Px_DR) Port x Data Direction Register (Px_DDR) Port x Alternate Register 1 (Px_ALT1) Port x Alternate Register 2 (Px_ALT2)
where x can be B, C, or D representing any of the three GPIO ports B, C, or D. The mode for each pin is controlled by setting each register bit pertinent to the pin to be configured. For example, the operating mode for Port B Pin 7 (PB7), is set by the values contained in PB_DR[7], PB_DDR[7], PB_ALT1[7], and PB_ALT2[7]. The combination of the GPIO control register bits allows individual configuration of each port pin for nine modes. In all modes, reading of the Port x Data register returns the sampled state, or level, of the signal on the corresponding pin. Table 7 indicates the function of each port signal based upon these four register bits. After a RESET event, all GPIO port pins are configured as standard digital inputs, with interrupts disabled.
Table 7. GPIO Mode Selection GPIO Mode 1 Px_ALT2 Bits7:0 0 0 2 0 0 Px_ALT1 Px_DDR Px_DR Bits7:0 Bits7:0 Bits7:0 Port Mode 0 0 0 0 0 0 1 1 0 1 0 1 Output Output Input from pin Input from pin
Output 0 1 High impedance High impedance
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Table 7. GPIO Mode Selection (Continued) GPIO Mode 3 Px_ALT2 Bits7:0 0 0 4 0 0 5 6 7 1 1 1 1 8 1 1 9 1 1 Px_ALT1 Px_DDR Px_DR Bits7:0 Bits7:0 Bits7:0 Port Mode 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Open-drain output Open-drain I/O Open-source I/O Open-source output Reserved Interrupt--dual edge triggered
Output 0 High impedance High impedance 1 High impedance High impedance
Port B, C, or D--alternate function controls port I/O. Port B, C, or D--alternate function controls port I/O. Interrupt--active Low Interrupt--active High High impedance High impedance
Interrupt--falling edge triggered High impedance Interrupt--rising edge triggered High impedance
GPIO Mode 1. The port pin is configured as a standard digital output pin. The value writ-
ten to the Port x Data register (Px_DR) is presented on the pin.
GPIO Mode 2. The port pin is configured as a standard digital input pin. The output is
tristated (high impedance). The value stored in the Port x Data register produces no effect. As in all modes, a Read from the Port x Data register returns the pin's value. GPIO Mode 2 is the default operating mode following a RESET.
GPIO Mode 3. The port pin is configured as open-drain I/O. The GPIO pins do not feature
an internal pull-up to the supply voltage. To employ the GPIO pin in OPEN-DRAIN mode, an external pull-up resistor must connect the pin to the supply voltage. Writing a 0 to the Port x Data register outputs a Low at the pin. Writing a 1 to the Port x Data register results in high-impedance output.
GPIO Mode 4. The port pin is configured as open-source I/O. The GPIO pins do not fea-
ture an internal pull-down to the supply ground. To employ the GPIO pin in OPENSOURCE mode, an external pull-down resistor must connect the pin to the supply ground. Writing a 1 to the Port x Data register outputs a High at the pin. Writing a 0 to the Port x Data register results in a high-impedance output.
GPIO Mode 5. Reserved. This pin produces high-impedance output.
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GPIO Mode 6. This bit enables a dual edge-triggered interrupt mode. Both a rising and a
falling edge on the pin cause an interrupt request to be sent to the CPU. Writing a 1 to the Port x Data register bit position resets the corresponding interrupt request. Writing a 0 produces no effect. The programmer must set the Port x Data register before entering the edge-triggered interrupt mode.
GPIO Mode 7. For Ports B, C, and D, the port pin is configured to pass control over to the
alternate (secondary) functions assigned to the pin. For example, the alternate mode function for PC7 is RI1 and the alternate mode function for PB4 is the Timer 4 Out. When GPIO Mode 7 is enabled, the pin output data and pin tristated control come from the alternate function's data output and tristate control, respectively. The value in the Port x Data register produces no effect on operation. Note: Input signals are sampled by the system clock before being passed to the alternate function input.
GPIO Mode 8. The port pin is configured for level-sensitive interrupt modes. An interrupt
request is generated when the level at the pin is the same as the level stored in the Port x Data register. The port pin value is sampled by the system clock. The input pin must be held at the selected interrupt level for a minimum of 2 clock periods to initiate an interrupt. The interrupt request remains active as long as this condition is maintained at the external source.
GPIO Mode 9. The port pin is configured for single edge-triggered interrupt mode. The
value in the Port x Data register determines if a positive or negative edge causes an interrupt request. A 0 in the Port x Data register bit sets the selected pin to generate an interrupt request for falling edges. A 1 in the Port x Data register bit sets the selected pin to generate an interrupt request for rising edges. The interrupt request remains active until a 1 is written to the corresponding interrupt request of the Port x Data register bit. Writing a 0 produces no effect on operation. The programmer must set the Port x Data register before entering the edge-triggered interrupt mode. A simplified block diagram of a GPIO port pin is illustrated in Figure 5.
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GPIO Register Data (Input) Q D Q D
System Clock VDD Mode 1 Mode 4 Data Bus System Clock GPIO Register Data (Output) Mode 1 Mode 3 GND D Q Port Pin
Figure 5.GPIO Port Pin Block Diagram
GPIO Interrupts
Each port pin can be used as an interrupt source. Interrupts can be either level- or edgetriggered. Level-Triggered Interrupts When the port is configured for level-triggered interrupts, the corresponding port pin is tristated. An interrupt request is generated when the level at the pin is the same as the level stored in the Port x Data register. The port pin value is sampled by the system clock. The input pin must be held at the selected interrupt level for a minimum of 2 consecutive clock cycles to initiate an interrupt. The interrupt request remains active as long as this condition is maintained at the external source. For example, if PD3 is programmed for low-level interrupt and the pin is forced Low for 2 consecutive clock cycles, an interrupt request signal is generated from that port pin and sent to the CPU. The interrupt request signal remains active until the external device driving PD3 forces the pin High. Edge-Triggered Interrupts When the port is configured for edge-triggered interrupts, the corresponding port pin is tristated. If the pin receives the correct edge from an external device, the port pin generates an interrupt request signal to the CPU. Any time a port pin is configured for edge-triggered
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interrupt, writing a 1 to that pin's Port x Data register causes a reset of the edge-detected interrupt. The programmer must set the bit in the Port x Data register to 1 before entering either single or dual edge-triggered interrupt mode for that port pin. When configured for dual edge-triggered interrupt mode (GPIO Mode 6), both a rising and a falling edge on the pin cause an interrupt request to be sent to the CPU. When configured for single edge-triggered interrupt mode (GPIO Mode 9), the value in the Port x Data register determines if a positive or negative edge causes an interrupt request. A 0 in the Port x Data register bit sets the selected pin to generate an interrupt request for falling edges. A 1 in the Port x Data register bit sets the selected pin to generate an interrupt request for rising edges.
GPIO Control Registers
The 12 GPIO Control Registers operate in groups of four with a set for each Port (B, C, and D). Each GPIO port features a Port Data register, Port Data Direction register, Port Alternate register 1, and Port Alternate register 2. Port x Data Registers When the port pins are configured for one of the output modes, the data written to the Port x Data registers, detailed in Table 8, are driven on the corresponding pins. In all modes, reading from the Port x Data registers always returns the current sampled value of the corresponding pins. When the port pins are configured as edge-triggered interrupt sources, writing a 1 to the corresponding bit in the Port x Data register clears the interrupt signal that is sent to the CPU. When the port pins are configured for edge-selectable interrupts or level-sensitive interrupts, the value written to the Port x Data register bit selects the interrupt edge or interrupt level. See Table 7 for more information.
Table 8. Port x Data Registers (PB_DR = 009Ah, PC_DR = 009Eh, PD_DR = 00A2h) Bit Reset CPU Access 7 X R/W 6 X R/W 5 X R/W 4 X R/W 3 X R/W 2 X R/W 1 X R/W 0 X R/W
Note: X = Undefined; R/W = Read/Write.
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Port x Data Direction Registers In conjunction with the other GPIO Control Registers, the Port x Data Direction registers, detailed in Table 9, control the operating modes of the GPIO port pins. See Table 7 for more information.
Table 9. Port x Data Direction Registers (PB_DDR = 009Bh, PC_DDR = 009Fh, PD_DDR = 00A3h) Bit Reset CPU Access
Note: R/W = Read/Write.
7 1 R/W
6 1 R/W
5 1 R/W
4 1 R/W
3 1 R/W
2 1 R/W
1 1 R/W
0 1 R/W
Port x Alternate Register 1 In conjunction with the other GPIO Control Registers, the Port x Alternate Register 1, detailed in Table 10, control the operating modes of the GPIO port pins. See Table 7 for more information.
Table 10. Port x Alternate Registers 1 (PB_ALT1 = 009Ch, PC_ALT1 = 00A0h, PD_ALT1 = 00A4h) Bit Reset CPU Access
Note: R/W = Read/Write.
7 0 R/W
6 0 R/W
5 0 R/W
4 0 R/W
3 0 R/W
2 0 R/W
1 0 R/W
0 0 R/W
Port x Alternate Register 2 In conjunction with the other GPIO Control Registers, the Port x Alternate Register 2, detailed in Table 11, control the operating modes of the GPIO port pins. See Table 7 for more information.
Table 11. Port x Alternate Registers 2 (PB_ALT2 = 009Dh, PC_ALT2 = 00A1h, PD_ALT2 = 00A5h) Bit Reset CPU Access
Note: R/W = Read/Write.
7 0 R/W
6 0 R/W
5 0 R/W
4 0 R/W
3 0 R/W
2 0 R/W
1 0 R/W
0 0 R/W
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Interrupt Controller
The interrupt controller on the EZ80F92 device routes the interrupt request signals from the internal peripherals and external devices (via the GPIO pins) to the CPU.
Maskable Interrupts
On the EZ80F92 device, all maskable interrupts use the CPU's vectored interrupt function. Table 12 lists the low-byte vector for each of the maskable interrupt sources. The maskable interrupt sources are listed in order of priority, with vector 00h being the highest-priority interrupt. The full 16-bit interrupt vector is located at starting address {I[7:0], IVECT[7:0]} where I[7:0] is the CPU's Interrupt Page Address Register.
Table 12. Interrupt Vector Sources by Priority Vector 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h Source Unused Unused Unused Unused Flash PRT 0 PRT 1 PRT 2 PRT 3 PRT 4 PRT 5 RTC UART 0 Vector 1Ah 1Ch 1Eh 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h Source UART 1 I2C SPI Unused Unused Unused Unused Unused Unused Unused Unused Port B 0 Port B 1 Vector 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Source Port B 2 Port B 3 Port B 4 Port B 5 Port B 6 Port B 7 Port C 0 Port C 1 Port C 2 Port C 3 Port C 4 Port C 5 Port C 6 Vector 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h Source Port C 7 Port D 0 Port D 1 Port D 2 Port D 3 Port D 4 Port D 5 Port D 6 Port D 7 Unused Unused Unused Unused
Note: Absolute locations 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h, and 66h are reserved for hardware reset, NMI, and the RST instruction.
The user's program should store the starting address of the interrupt service routine (ISR) in the two-byte interrupt vector locations. For example, for ADL mode the two-byte address for the SPI interrupt service routine would be stored at {00h, I[7:0], 1Eh} and {00h, I[7:0], 1Fh}. In Z80 mode, the two-byte address for the SPI interrupt service rou-
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tine would be stored at {MBASE[7:0], I[7:0], 1Eh} and {MBASE, I[7:0], 1Fh}. The leastsignificant byte is stored at the lower address. When any one or more of the interrupt requests (IRQs) become active, an interrupt request is generated by the interrupt controller and sent to the CPU. The corresponding 8-bit interrupt vector for the highest-priority interrupt is placed on the 8-bit interrupt vector bus, IVECT[7:0]. The interrupt vector bus is internal to the EZ80F92 device and is therefore not visible externally. The response time of the CPU to an interrupt request is a function of the current instruction being executed as well as the number of wait states being asserted. The interrupt vector, {I[7:0], IVECT[7:0]}, is visible on the address bus, ADDR[15:0], when the interrupt service routine begins. The response of the CPU to a vectored interrupt on the EZ80F92 device is explained in Table 13. Interrupt sources are required to be active until the interrupt service routine starts. It is recommended that the Interrupt Page Address Register (I) value be changed by the user from its default value of 00h as this address can create conflicts between the nonmaskable interrupt vector, the RST instruction addresses, and the maskable interrupt vectors.
Table 13. Vectored Interrupt Operation Memory Mode Z80 Mode ADL Bit 0 MADL Bit Operation 0 Read the LSB of the interrupt vector placed on the internal vectored interrupt bus, IVECT [7:0], by the interrupting peripheral. * IEF1 0 * IEF2 0 * The Starting Program Counter is effectively {MBASE, PC[15:0]} * Push the 2-byte return address PC[15:0] onto the ({MBASE,SPS}) stack * The ADL mode bit remains cleared to 0 * The interrupt vector address is located at {MBASE, I[7:0], IVECT[7:0]} * PC[15:0] ({MBASE, I[7:0], IVECT[7:0]}) * The ending Program Counter is effectively {MBASE, PC[15:0]} * The interrupt service routine must end with RETI Read the LSB of the interrupt vector placed on the internal vectored interrupt bus, IVECT [7:0], by the interrupting peripheral. * IEF1 0 * IEF2 0 * The Starting Program Counter is PC[23:0] * Push the 3-byte return address, PC[23:0], onto the SPL stack * The ADL mode bit remains set to 1 * The interrupt vector address is located at {00h, I[7:0], IVECT[7:0]} * PC[15:0] ({00h, I[7:0], IVECT[7:0]}) * The ending Program Counter is {00h, PC[15:0]} * The interrupt service routine must end with RETI
ADL Mode
1
0
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Table 13. Vectored Interrupt Operation (Continued) Memory Mode Z80 Mode ADL Bit 0 MADL Bit Operation 1 Read the LSB of the interrupt vector placed on the internal vectored interrupt bus, IVECT[7:0], bus by the interrupting peripheral. * IEF1 0 * IEF2 0 * The Starting Program Counter is effectively {MBASE, PC[15:0]} * Push the 2-byte return address, PC[15:0], onto the SPL stack * Push a 00h byte onto the SPL stack to indicate an interrupt from Z80 mode (because ADL = 0) * Set the ADL mode bit to 1 * The interrupt vector address is located at {00h, I[7:0], IVECT[7:0]} * PC[15:0] ({00h, I[7:0], IVECT[7:0]}) * The ending Program Counter is {00h, PC[15:0]} * The interrupt service routine must end with RETI.L Read the LSB of the interrupt vector placed on the internal vectored interrupt bus, IVECT [7:0], by the interrupting peripheral. * IEF1 0 * IEF2 0 * The Starting Program Counter is PC[23:0] * Push the 3-byte return address, PC[23:0], onto the SPL stack * Push a 01h byte onto the SPL stack to indicate a restart from ADL mode (because ADL = 1) * The ADL mode bit remains set to 1 * The interrupt vector address is located at {00h, I[7:0], IVECT[7:0]} * PC[15:0] ({00h, I[7:0], IVECT[7:0]}) * The ending Program Counter is {00h, PC[15:0]} * The interrupt service routine must end with RETI.L
ADL Mode
1
1
Nonmaskable Interrupts
An active Low input on the NMI pin generates an interrupt request to the CPU. This nonmaskable interrupt is always serviced by the CPU regardless of the state of the Interrupt Enable flags (IEF1 and IEF2). The nonmaskable interrupt is prioritized higher than all maskable interrupts. The response of the CPU to a nonmaskable interrupt is described in detail in the eZ80 CPU User Manual (UM0077).
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Chip Selects and Wait States
The EZ80F92 device generates four Chip Selects for external devices. Each Chip Select may be programmed to access either memory space or I/O space. The Memory Chip Selects can be individually programmed on a 64 KB boundary. The I/O Chip Selects can each choose a 256-byte section of I/O space. In addition, each Chip Select may be programmed for up to 7 wait states.
Memory and I/O Chip Selects
Each of the Chip Selects can be enabled for either the memory address space or the I/O address space, but not both. To select the memory address space for a particular Chip Select, CSX_IO (CSx_CTL[4]) must be reset to 0. To select the I/O address space for a particular Chip Select, CSX_IO must be set to 1. After RESET, the default is for all Chip Selects to be configured for the memory address space. For either the memory address space or the I/O address space, the individual Chip Selects must be enabled by setting CSx_EN (CSx_CTL[3]) to 1.
Memory Chip Select Operation
Operation of each of the Memory Chip Selects is controlled by three control registers. To enable a particular Memory Chip Select, the following conditions must be met:
* * * * * * * *
The Chip Select is enabled by setting CSx_EN to 1 The Chip Select is configured for Memory by clearing CSX_IO to 0 The address is in the associated Chip Select range:
CSx_LBR[7:0] ADDR[23:16] CSx_UBR[7:0]
No higher priority (lower number) Chip Select meets the above conditions A memory access instruction must be executing
If all of the foregoing conditions are met to generate a Memory Chip Select, then the following actions occur: The appropriate Chip Select--CS0, CS1, CS2, or CS3--is asserted (driven Low) MREQ is asserted (driven Low) Depending upon the instruction, either RD or WR is asserted (driven Low)
If the upper and lower bounds are set to the same value (CSx_UBR = CSx_LBR), then a particular Chip Select is valid for a single 64 KB page.
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Memory Chip Select Priority A lower-numbered Chip Select is granted priority over a higher-numbered Chip Select. For example, if the address space of Chip Select 0 overlaps the Chip Select 1 address space, Chip Select 0 is active. Reset States On RESET, Chip Select 0 is active for all addresses, because its Lower Bound register resets to 00h and its Upper Bound register resets to FFh. All of the other Chip Select Lower and Upper Bound registers reset to 00h. Memory Chip Select Example The use of Memory Chip Selects is demonstrated in Figure 6. The associated control register values indicated in Table 14. In this example, all 4 Chip Selects are enabled and configured for memory addresses. Also, CS1 overlaps with CS0. Because CS0 is prioritized higher than CS1, CS1 is not active for much of its defined address space.
Memory Location CS3_UBR = FFh CS3_LBR = D0h CS2_UBR = CFh CS2_LBR = A0h CS1_UBR = 9Fh CS3 Active 3 MB Address Space CS2 Active 3 MB Address Space CS1 Active 2 MB Address Space FFFFFFh D00000h CFFFFFh A00000h 9FFFFFh 800000h 7FFFFFh
CS0_UBR = 7Fh
CS0 Active 8 MB Address Space
CS0_LBR = CS1_LBR = 00h
000000h
Figure 6.Example: Memory Chip Select
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Table 14. Register Values for Memory Chip Select Example in Figure 6 Chip CSx_CTL[3] CSx_CTL[4] Select CSx_EN CSx_IO CSx_LBR CSx_UBR Description CS0 1 0 00h 7Fh CS0 is enabled as a Memory Chip Select. Valid addresses range from 000000h- 7FFFFFh. CS1 is enabled as a Memory Chip Select. Valid addresses range from 800000h- 9FFFFFh. CS2 is enabled as a Memory Chip Select. Valid addresses range from A00000h- CFFFFFh. CS3 is enabled as a Memory Chip Select. Valid addresses range from D00000h- FFFFFFh.
CS1
1
0
00h
9Fh
CS2
1
0
A0h
CFh
CS3
1
0
D0h
FFh
I/O Chip Select Operation
I/O Chip Selects can only be active when the CPU is performing I/O instructions. Because the I/O space is separate from the memory space in the EZ80F92 device, there can never be a conflict between I/O and memory addresses. The EZ80F92 device supports a 16-bit I/O address. The I/O Chip Select logic decodes the High byte of the I/O address, ADDR[15:8]. Because the upper byte of the address bus, ADDR[23:16], is ignored, the I/O devices can always be accessed from within any memory mode (ADL or Z80). The MBASE offset value used for setting the Z80 MEMORY mode page is also always ignored. Four I/O Chip Selects are available with the EZ80F92 device. To generate a particular I/O Chip Select, the following conditions must be met:
* * * * *
The Chip Select is enabled by setting CSX_EN to 1 The Chip Select is configured for I/O by setting CSX_IO to 1 An I/O Chip Select address match occurs--ADDR[15:8] = CSx_LBR[7:0] No higher-priority (lower-number) Chip Select meets the above conditions The I/O address is not within the on-chip peripheral address range 0080h-00FFh. On-chip peripheral registers assume priority for all addresses where:
0080h ADDR[15:0] 00FFh
*
An I/O instruction must be executing
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If all of the foregoing conditions are met to generate an I/O Chip Select, then the following actions occur:
* * *
The appropriate Chip Select--CS0, CS1, CS2, or CS3--is asserted (driven Low) IORQ is asserted (driven Low) Depending upon the instruction, either RD or WR is asserted (driven Low)
WAIT States
For each of the Chip Selects, programmable WAIT states can be asserted to provide external devices with additional clock cycles to complete their Read or Write operations. The number of WAIT states for a particular Chip Select is controlled by the 3-bit field CSx_WAIT (CSx_CTL[7:5]). The WAIT states can be independently programmed to provide 0 to 7 WAIT states for each Chip Select. The WAIT states idle the CPU for the specified number of system clock cycles.
WAIT Input Signal
Similar to the programmable WAIT states, an external peripheral can drive the WAIT input pin to force the CPU to provide additional clock cycles to complete its Read or Write operation. Driving the WAIT pin Low stalls the CPU. The CPU resumes operation on the first rising edge of the internal system clock following deassertion of the WAIT pin. Caution: If the WAIT pin is to be driven by an external device, the corresponding Chip Select for the device must be programmed to provide at least one WAIT state. Due to input sampling of the WAIT input pin (shown in Figure 7), one programmable WAIT state is required to allow the external peripheral sufficient time to assert the WAIT pin. It is recommended that the corresponding Chip Select for the external device be programmed to provide the maximum number of WAIT states (seven).
Wait Pin
D
Q
eZ80 CPU
System Clock
Figure 7.Wait Input Sampling Block Diagram
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An example of WAIT state operation is illustrated in Figure 8. In this example, the Chip Select is configured to provide a single WAIT state. The external peripheral being accessed drives the WAIT pin Low to request assertion of an additional WAIT state. If the WAIT pin is asserted for additional system clock cycles, WAIT states are added until the WAIT pin is deasserted (High).
TCLK
X IN
TWAIT
ADDR[23:0]
DATA[7:0] (output)
CSx
MREQ
RD
INSTRD
Figure 8.Example: Wait State Operation Read Operation
Chip Selects During Bus Request/Bus Acknowledge Cycles
When the CPU relinquishes the address bus to an external peripheral in response to an external bus request (BUSREQ), it drives the bus acknowledge pin (BUSACK) Low. The external peripheral can then drive the address bus (and data bus). The CPU continues to generate Chip Select signals in response to the address on the bus. External devices cannot access the internal registers of the EZ80F92 device.
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Bus Mode Controller
The bus mode controller allows the address and data bus timing and signal formats of the EZ80F92 device to be configured to connect seamlessly with external eZ80(R), Z80-, Intel-, or Motorola-compatible devices. Bus modes for each of the chip selects can be configured independently using the Chip Select Bus Mode Control Registers. The number of CPU system clock cycles per bus mode state is also independently programmable. For IntelTM bus mode, multiplexed address and data can be selected in which the lower byte of the address and the data byte both use the data bus, DATA[7:0]. Each of the bus modes is explained in more detail in the following sections.
eZ80 Bus Mode
Chip selects configured for eZ80 bus mode do not modify the bus signals from the CPU. The timing diagrams for external Memory and I/O Read and Write operations are shown in the AC Characteristics section on page 228. The default mode for each chip select is eZ80 mode.
Z80 Bus Mode
Chip selects configured for Z80 mode modify the CPU bus signals to match the Z80 microprocessor address and data bus interface signal format and timing. During read operations, the Z80 bus mode employs three states (T1, T2, and T3) as described in Table 15.
Table 15. Z80 Bus Mode Read States STATE T1 STATE T2 The Read cycle begins in State T1. The CPU drives the address onto the address bus and the associated Chip Select signal is asserted. During State T2, the RD signal is asserted. Depending upon the instruction, either the MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU system clock cycle prior to the end of State T2, additional WAIT states (TWAIT) are asserted until the WAIT pin is driven High. During State T3, no bus signals are altered. The data is latched by the EZ80F92 device at the rising edge of the CPU system clock at the end of State T3.
STATE T3
During Write operations, Z80 bus mode employs 3 states (T1, T2, and T3) as described in Table 16.
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Table 16. Z80 Bus Mode Write States STATE T1 STATE T2 The Write cycle begins in State T1. The CPU drives the address onto the address bus, the associated Chip Select signal is asserted. During State T2, the WR signal is asserted. Depending upon the instruction, either the MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU system clock cycle prior to the end of State T2, additional WAIT states (TWAIT) are asserted until the WAIT pin is driven High. During State T3, no bus signals are altered.
STATE T3
Z80 bus mode Read and Write timing is illustrated in Figures 9 and 10 . The Z80 bus mode states can be configured for 1 to 15 CPU system clock cycles. In the figures, each Z80 bus mode state is two CPU system clock cycles in duration. Figures 9 and 10 also illustrate the assertion of 1 wait state (TWAIT) by the external peripheral during each Z80 bus mode cycle.
T1 System Clock T2 TCLK T3
ADDR[23:0]
DATA[7:0]
CSx
RD
WAIT
WR
MREQ or IORQ
Figure 9.Example: Z80 Bus Mode Read Timing
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T1 System Clock
T2
TCLK
T3
ADDR[23:0]
DATA[7:0]
CSx
RD
WAIT
WR
MREQ or IORQ
Figure 10.Example: Z80 Bus Mode Write Timing
IntelTM Bus Mode
Chip selects configured for IntelTM bus mode modify the CPU bus signals to duplicate a four-state memory transfer similar to that found on Intel-style microcontrollers. The bus signals and EZ80F92 device pins are mapped as illustrated in Figure 11. In IntelTM bus mode, the user can select either multiplexed or nonmultiplexed address and data buses. In nonmultiplexed operation, the address and data buses are separate. In multiplexed operation, the lower byte of the address, ADDR[7:0], also appears on the data bus, DATA[7:0], during State T1 of the IntelTM bus mode cycle. During multiplexed operation, the lower byte of the address bus also appears on the address bus in addition to the data bus.
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Bus Mode Controller eZ80 Bus Mode Signals (Pins) INSTRD RD WR WAIT MREQ IORQ ADDR[23:0] ADDR[7:0] Multiplexed Bus Controller Intel Bus Signal Equvalents ALE RD WR READY MREQ IORQ ADDR[23:0]
DATA[7:0]
DATA[7:0]
Figure 11.IntelTM Bus Mode Signal and Pin Mapping
IntelTM Bus Mode (Separate Address and Data Buses) During Read operations with separate address and data buses, the IntelTM bus mode employs 4 states (T1, T2, T3, and T4) as described in Table 17.
Table 17. IntelTM Bus Mode Read States (Separate Address and Data Buses) STATE T1 The Read cycle begins in State T1. The CPU drives the address onto the address bus and the associated Chip Select signal is asserted. The CPU drives the ALE signal High at the beginning of T1. During the middle of T1, the CPU drives ALE Low to facilitate the latching of the address. During State T2, the CPU asserts the RD signal. Depending on the instruction, either the MREQ or IORQ signal is asserted.
STATE T2
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Table 17. IntelTM Bus Mode Read States (Separate Address and Data Buses) STATE T3 During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low at least one CPU system clock cycle prior to the beginning of State T3, additional wait states (TWAIT) are asserted until the READY pin is driven High. The CPU latches the Read data at the beginning of State T4. The CPU deasserts the RD signal and completes the IntelTM bus mode cycle.
STATE T4
During Write operations with separate address and data buses, the IntelTM bus mode employs 4 states (T1, T2, T3, and T4) as described in Table 18.
Table 18. IntelTM Bus Mode Write States (Separate Address and Data Buses) STATE T1 The Write cycle begins in State T1. The CPU drives the address onto the address bus, the associated Chip Select signal is asserted, and the data is driven onto the data bus. The CPU drives the ALE signal High at the beginning of T1. During the middle of T1, the CPU drives ALE Low to facilitate the latching of the address. During State T2, the CPU asserts the WR signal. Depending on the instruction, either the MREQ or IORQ signal is asserted. During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low at least one CPU system clock cycle prior to the beginning of State T3, additional WAIT states (TWAIT) are asserted until the READY pin is driven High. The CPU deasserts the WR signal at the beginning of State T4. The CPU holds the data and address buses through the end of T4. The bus cycle is completed at the end of T4.
STATE T2 STATE T3
STATE T4
IntelTM bus mode timing is illustrated for a Read operation in Figure 12 and for a Write operation in Figure 13. If the READY signal (external WAIT pin) is driven Low prior to the beginning of State T3, additional wait states (TWAIT) are asserted until the READY signal is driven High. The IntelTM bus mode states can be configured for 2 to 15 CPU system clock cycles. In the figures, each IntelTM bus mode state is 2 CPU system clock cycles in duration. Figures 12 and 13 also illustrate the assertion of one WAIT state (TWAIT) by the selected peripheral.
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T1 System Clock
T2
T3
TWAIT
T4
ADDR[23:0]
DATA[7:0]
CSx
ALE
RD
READY
WR
MREQ or IORQ
Figure 12.Example: IntelTM Bus Mode Read Timing--Separate Address and Data Buses
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T1 System Clock
T2
T3
TWAIT
T4
ADDR[23:0]
DATA[7:0]
CSx
ALE
WR
READY
RD
MREQ or IORQ
Figure 13.Example: IntelTM Bus Mode Write Timing--Separate Address and Data Buses
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IntelTM Bus Mode (Multiplexed Address and Data Bus) During Read operations with multiplexed address and data, the IntelTM bus mode employs 4 states (T1, T2, T3, and T4) as described in Table 19.
Table 19. IntelTM Bus Mode Read States (Multiplexed Address and Data Bus) STATE T1 The Read cycle begins in State T1. The CPU drives the address onto the DATA bus and the associated Chip Select signal is asserted. The CPU drives the ALE signal High at the beginning of T1. During the middle of T1, the CPU drives ALE Low to facilitate the latching of the address. During State T2, the CPU removes the address from the DATA bus and asserts the RD signal. Depending upon the instruction, either the MREQ or IORQ signal is asserted. During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low at least one CPU system clock cycle prior to the beginning of State T3, additional WAIT states (TWAIT) are asserted until the READY pin is driven High. The CPU latches the Read data at the beginning of State T4. The CPU deasserts the RD signal and completes the IntelTM bus mode cycle.
STATE T2
STATE T3
STATE T4
During Write operations with multiplexed address and data, the IntelTM bus mode employs 4 states (T1, T2, T3, and T4) as described in Table 20.
Table 20. IntelTM Bus Mode Write States (Multiplexed Address and Data Bus) STATE T1 The Write cycle begins in State T1. The CPU drives the address onto the DATA bus and drives the ALE signal High at the beginning of T1. During the middle of T1, the CPU drives ALE Low to facilitate the latching of the address. During State T2, the CPU removes the address from the DATA bus and drives the Write data onto the DATA bus. The WR signal is asserted to indicate a Write operation. During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low at least one CPU system clock cycle prior to the beginning of State T3, additional wait states (TWAIT) are asserted until the READY pin is driven High. The CPU deasserts the Write signal at the beginning of T4 identifying the end of the Write operation. The CPU holds the data and address buses through the end of T4. The bus cycle is completed at the end of T4.
STATE T2
STATE T3
STATE T4
Signal timing for IntelTM bus mode with multiplexed address and data is illustrated for a Read operation in Figure 14 and for a Write operation in Figure 15. In the figures, each
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IntelTM bus mode state is 2 CPU system clock cycles in duration. Figures 14 and 15 also illustrate the assertion of one wait state (TWAIT) by the selected peripheral.
T1 System Clock
T2
T3
TWAIT
T4
ADDR[23:0]
DATA[7:0]
CSx
ALE
RD
READY
WR
MREQ or IORQ
Figure 14.Example: IntelTM Bus Mode Read Timing--Multiplexed Address and Data Bus
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T1 System Clock
T2
T3
TWAIT
T4
ADDR[23:0]
DATA[7:0]
CSx
ALE
WR
READY
RD
MREQ or IORQ
Figure 15.Example: IntelTM Bus Mode Write Timing--Multiplexed Address and Data Bus
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Motorola Bus Mode
Chip selects configured for Motorola bus mode modify the CPU bus signals to duplicate an eight-state memory transfer similar to that found on Motorola-style microcontrollers. The bus signals (and EZ80F92 I/O pins) are mapped as illustrated in Figure 16.
Bus Mode Controller eZ80 Bus Mode Signals (Pins) INSTRD RD WR WAIT MREQ IORQ ADDR[23:0] DATA[7:0] Motorola Bus Signal Equvalents AS DS R/W DTACK MREQ IORQ ADDR[23:0] DATA[7:0]
Figure 16.Motorola Bus Mode Signal and Pin Mapping
During Write operations, the Motorola bus mode employs 8 states (S0, S1, S2, S3, S4, S5, S6, and S7) as described in Table 21.
Table 21. Motorola Bus Mode Read States STATE S0 STATE S1 STATE S2 STATE S3 The Read cycle starts in state S0. The CPU drives R/W High to identify a Read cycle. Entering state S1, the CPU drives a valid address on the address bus, ADDR[23:0]. On the rising edge of state S2, the CPU asserts AS and DS. During state S3, no bus signals are altered.
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Table 21. Motorola Bus Mode Read States (Continued) STATE S4 During state S4, the CPU waits for a cycle termination signal DTACK (WAIT), a peripheral signal. If the termination signal is not asserted at least one full CPU clock period prior to the rising clock edge at the end of S4, the CPU inserts WAIT (TWAIT) states until DTACK is asserted. Each WAIT state is a full bus mode cycle. During state S5, no bus signals are altered. During state S6, data from the external peripheral device is driven onto the data bus. On the rising edge of the clock entering state S7, the CPU latches data from the addressed peripheral device and deasserts AS and DS. The peripheral device deasserts DTACK at this time.
STATE S5 STATE S6 STATE S7
The eight states for a Write operation in Motorola bus mode are described in Table 22.
Table 22. Motorola Bus Mode Write States STATE S0 STATE S1 STATE S2 STATE S3 STATE S4 The Write cycle starts in S0. The CPU drives R/W High (if a preceding Write cycle leaves R/W Low). Entering S1, the CPU drives a valid address on the address bus. On the rising edge of S2, the CPU asserts AS and drives R/W Low. During S3, the data bus is driven out of the high-impedance state as the data to be written is placed on the bus. At the rising edge of S4, the CPU asserts DS. The CPU waits for a cycle termination signal DTACK (WAIT). If the termination signal is not asserted at least one full CPU clock period prior to the rising clock edge at the end of S4, the CPU inserts WAIT (TWAIT) states until DTACK is asserted. Each WAIT state is a full bus mode cycle. During S5, no bus signals are altered. During S6, no bus signals are altered. Upon entering S7, the CPU deasserts AS and DS. As the clock rises at the end of S7, the CPU drives R/W High. The peripheral device deasserts DTACK at this time.
STATE S5 STATE S6 STATE S7
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Signal timing for Motorola bus mode is illustrated for a Read operation in Figure 17 and for a Write operation in Figure 18. In these two figures, each Motorola bus mode state is 2 CPU system clock cycles in duration.
S0
S1
S2
S3
S4
S5
S6
S7
System Clock
ADDR[23:0]
DATA[7:0]
CSx
AS
DS
R/W
DTACK
MREQ or IORQ
Figure 17.Example: Motorola Bus Mode Read Timing
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S0
S1
S2
S3
S4
S5
S6
S7
System Clock
ADDR[23:0]
DATA[7:0]
CSx
AS
DS
R/W
DTACK
MREQ or IORQ
Figure 18.Example: Motorola Bus Mode Write Timing
Switching Between Bus Modes Each time the bus mode controller must switch from one bus mode to another, there is a one-cycle CPU system clock delay. An extra clock cycle is not required for repeated access in any of the bus modes; nor is it required when the EZ80F92 device switches to eZ80 bus mode. The extra clock cycles are not shown in the timing examples. Due to the asynchronous nature of these bus protocols, the extra delay does not impact peripheral communication.
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Chip Select Registers
Chip Select x Lower Bound Register For Memory Chip Selects, the Chip Select x Lower Bound register, detailed in Table 23, defines the lower bound of the address range for which the corresponding Memory Chip Select (if enabled) can be active. For I/O Chip Selects, this register defines the address to which ADDR[15:8] is compared to generate an I/O Chip Select. All Chip Select lower bound registers reset to 00h.
Table 23. Chip Select x Lower Bound Register (CS0_LBR = 00A8h, CS1_LBR = 00ABh, CS2_LBR = 00AEh, CS3_LBR = 00B1h) Bit CS0_LBR Reset CS1_LBR Reset CS2_LBR Reset CS3_LBR Reset CPU Access
Note: R/W = Read/Write.
7 0 0 0 0 R/W
6 0 0 0 0 R/W
5 0 0 0 0 R/W
4 0 0 0 0 R/W
3 0 0 0 0 R/W
2 0 0 0 0 R/W
1 0 0 0 0 R/W
0 0 0 0 0 R/W
Bit Position [7:0] CSx_LBR
Value Description 00h- FFh For Memory Chip Selects (CSX_IO = 0) This byte specifies the lower bound of the Chip Select address range. The upper byte of the address bus, ADDR[23:16], is compared to the values contained in these registers for determining whether a Memory Chip Select signal should be generated. For I/O Chip Selects (CSX_IO = 1) This byte specifies the Chip Select address value. ADDR[15:8] is compared to the values contained in these registers for determining whether an I/O Chip Select signal should be generated.
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Chip Select x Upper Bound Register For Memory Chip Selects, the Chip Select x Upper Bound registers, detailed in Table 24, defines the upper bound of the address range for which the corresponding Chip Select (if enabled) can be active. For I/O Chip Selects, this register produces no effect. The reset state for the Chip Select 0 Upper Bound register is FFh, while the reset state for the other Chip Select upper bound registers is 00h.
Table 24. Chip Select x Upper Bound Register (CS0_UBR = 00A9h, CS1_UBR = 00ACh, CS2_UBR = 00AFh, CS3_UBR = 00B2h) Bit CS0_UBR Reset CS1_UBR Reset CS2_UBR Reset CS3_UBR Reset CPU Access
Note: R/W = Read/Write.
7 1 0 0 0 R/W
6 1 0 0 0 R/W
5 1 0 0 0 R/W
4 1 0 0 0 R/W
3 1 0 0 0 R/W
2 1 0 0 0 R/W
1 1 0 0 0 R/W
0 1 0 0 0 R/W
Bit Position [7:0] CSx_UBR
Value Description 00h- FFh For Memory Chip Selects (CSx_IO = 0) This byte specifies the upper bound of the Chip Select address range. The upper byte of the address bus, ADDR[23:16], is compared to the values contained in these registers for determining whether a Chip Select signal should be generated. For I/O Chip Selects (CSx_IO = 1) No effect.
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Chip Select x Control Register The Chip Select x Control register, detailed in Table 25, enables the Chip Selects, specifies the type of Chip Select, and sets the number of WAIT states. The reset state for the Chip Select 0 Control register is E8h, while the reset state for the 3 other Chip Select control registers is 00h.
Table 25. Chip Select x Control Register (CS0_CTL = 00AAh, CS1_CTL = 00ADh, CS2_CTL = 00B0h, CS3_CTL = 00B3h) Bit CS0_CTL Reset CS1_CTL Reset CS2_CTL Reset CS3_CTL Reset CPU Access 7 1 0 0 0 R/W 6 1 0 0 0 R/W 5 1 0 0 0 R/W 4 0 0 0 0 R/W 3 1 0 0 0 R/W 2 0 0 0 0 R 1 0 0 0 0 R 0 0 0 0 0 R
Note: R/W = Read/Write; R = Read Only.
Bit Position [7:5] CSx_WAIT
Value Description 000 001 010 011 100 101 110 111 0 WAIT states are asserted when this Chip Select is active. 1 WAIT state is asserted when this Chip Select is active. 2 WAIT states are asserted when this Chip Select is active. 3 WAIT states are asserted when this Chip Select is active. 4 WAIT states are asserted when this Chip Select is active. 5 WAIT states are asserted when this Chip Select is active. 6 WAIT states are asserted when this Chip Select is active. 7 WAIT states are asserted when this Chip Select is active. Chip Select is configured as a Memory Chip Select. Chip Select is configured as an I/O Chip Select. Chip Select is disabled. Chip Select is enabled. Reserved.
4
0 1 0 1 000
CSX_IO
3 CSx_EN [2:0]
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Chip Select x Bus Mode Control Register+The Chip Select Bus Mode register, detailed in Table 26, configures the Chip Select for eZ80, Z80, IntelTM, or Motorola bus modes. Changing the bus mode allows the EZ80F92 device to interface to peripherals based on the Z80-, Intel-, or Motorola-style asynchronous bus interfaces. When a bus mode other than CPU is programmed for a particular Chip Select, the CSx_WAIT setting in that Chip Select Control Register is ignored.
Table 26. Chip Select x Bus Mode Control Register (CS0_BMC = 00F0h, CS1_BMC = 00F1h, CS2_BMC = 00F2h, CS3_BMC = 00F3h) Bit CS0_BMC Reset CS1_BMC Reset CS2_BMC Reset CS3_BMC Reset CPU Access 7 0 0 0 0 R/W 6 0 0 0 0 R/W 5 0 0 0 0 R/W 4 0 0 0 0 R 3 0 0 0 0 R/W 2 0 0 0 0 R/W 1 1 1 1 1 R/W 0 0 0 0 0 R/W
Note: R/W = Read/Write; R = Read Only.
Bit Position [7:6] BUS_MODE
Value Description 00 01 10 11 eZ80 bus mode. Z80 bus mode. IntelTM bus mode. Motorola bus mode. Separate address and data. Multiplexed address and data--appears on data bus DATA[7:0]. Reserved.
5 AD_MUX
0 1 0
4
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Bit Position [3:0] BUS_CYCLE
Value Description 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Not valid. Each bus mode state is 1 CPU clock cycle in duration.1, 2, 3 Each bus mode state is 2 CPU clock cycles in duration. Each bus mode state is 3 CPU clock cycles in duration. Each bus mode state is 4 CPU clock cycles in duration. Each bus mode state is 5 CPU clock cycles in duration. Each bus mode state is 6 CPU clock cycles in duration. Each bus mode state is 7 CPU clock cycles in duration. Each bus mode state is 8 CPU clock cycles in duration. Each bus mode state is 9 CPU clock cycles in duration. Each bus mode state is 10 CPU clock cycles in duration. Each bus mode state is 11 CPU clock cycles in duration. Each bus mode state is 12 CPU clock cycles in duration. Each bus mode state is 13 CPU clock cycles in duration. Each bus mode state is 14 CPU clock cycles in duration. Each bus mode state is 15 CPU clock cycles in duration.
Notes: 1. Setting BUS_CYCLE to 1 in IntelTM bus mode causes the ALE pin to not function properly. 2. Use of the external WAIT input pin in Z80 mode requires that BUS_CYCLE is set to a value greater than 1. 3. BUS_CYCLE produces no effect in eZ80 mode.
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Watch-Dog Timer
Watch-Dog Timer Overview
The Watch-Dog Timer (WDT) helps protect against corrupt or unreliable software, power faults, and other system-level problems which may place the CPU into unsuitable operating states. The EZ80F92 WDT features:
* * * *
Four programmable time-out periods: 218, 222, 225, and 227 clock cycles Two selectable WDT clock sources: the system clock or the Real-Time Clock source (on-chip 32 KHz crystal oscillator or 50/60 Hz signal) A selectable time-out response: a time-out can be configured to generate either a RESET or a nonmaskable interrupt (NMI) A WDT time-out RESET indicator flag
Figure 19 illustrates the block diagram for the Watch-Dog Timer.
Data[7:0]
Control Register/ Reset Register WDT_CLK
RTC Clock 28-Bit Upcounter System Clock WDT Control Logic
Time-out Compare Logic (WDT_PERIOD) RESET NMI to eZ80 CPU
Figure 19.Watch-Dog Timer Block Diagram
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Watch-Dog Timer Operation
Enabling and Disabling the WDT The Watch-Dog Timer is disabled upon a RESET. To enable the WDT, the application program must set the WDT_EN bit (bit 7) of the WDT_CTL register. When enabled, the WDT cannot be disabled without a RESET. Time-Out Period Selection There are four choices of time-out periods for the WDT--218, 222, 225, and 227 system clock cycles. The WDT time-out period is defined by the WDT_PERIOD field of the WDT_CTL register (WDT_CTL[1:0]). The approximate time-out periods for two different WDT clock sources is listed in Table 27.
Table 27. Watch-Dog Timer Approximate Time-Out Delays Clock Source 32.768 KHz Crystal Oscillator 32.768 KHz Crystal Oscillator 32.768 KHz Crystal Oscillator 32.768 KHz Crystal Oscillator 20 MHz System Clock 20 MHz System Clock 20 MHz System Clock 20 MHz System Clock 50 MHz System Clock 50 MHz System Clock 50 MHz System Clock 50 MHz System Clock Divider Value 218 222 225 227 218 222 225 227 218 222 225 227 Time Out Delay 8.00 s 128 s 1024 s 4096 s 13.1 ms* 209.7 ms* 1.68 s 6.71 s 5.2 ms 83.9 ms 0.67 s 2.68 s
Note: *WDT time-out values should be sufficiently long to allow Flash operations to complete.
RESET Or NMI Generation Upon a WDT time-out, the RST_FLAG bit in the WDT_CTL register is set to 1. In addition, the WDT can cause a RESET or send a nonmaskable interrupt (NMI) signal to the CPU. The default operation is for the WDT to cause a RESET. It asserts/deasserts on the rising edge of the clock. The RST_FLAG bit can be polled by the CPU to determine the source of the RESET event.
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EZ80F92/eZ80F93 Product Specification
75
If the NMI_OUT bit in the WDT_CTL register is set to 1, then upon time-out, the WDT asserts an NMI for CPU processing. The NMI_FLAG bit can be polled by the CPU to determine the source of the NMI event.
Watch-Dog Timer Registers
Watch-Dog Timer Control Register The Watch-Dog Timer Control register, detailed in Table 28, is an 8-bit Read/Write register used to enable the Watch-Dog Timer, set the time-out period, indicate the source of the most recent RESET, and select the required operation upon WDT time-out.
Table 28. Watch-Dog Timer Control Register (WDT_CTL = 0093h) Bit Reset CPU Access 7 0 R/W 6 0 R/W 5 0/1 R 4 0 R/W 3 0 R/W 2 0 R 1 0 R/W 0 0 R/W
Note: R = Read only; R/W = Read/Write.
Bit Position 7 WDT_EN
Value Description 0 1 0 1 0 1 WDT is disabled. WDT is enabled. When enabled, the WDT cannot be disabled without a RESET. WDT time-out resets the CPU. WDT time-out generates a nonmaskable interrupt (NMI) to the CPU. RESET caused by external full-chip reset or ZDI reset. RESET caused by WDT time-out. This flag is set by the WDT time-out, even if the NMI_OUT flag is set to 1. The CPU can poll this bit to determine the source of the RESET or NMI. WDT clock source is system clock. WDT clock source is Real-Time Clock source (32 KHz on-chip oscillator or 50/60Hz input as set by RTC_CTRL[4]). Reserved. Reserved. Reserved.
6 NMI_OUT
5 RST_FLAG*
[4:3] WDT_CLK
00 01 10 11
2
0
Note: *RST_FLAG is only cleared by a non-WDT RESET.
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Watch-Dog Timer
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Bit Position [1:0] WDT_PERIOD
Value Description 00 01 10 11 WDT time-out period is 227 clock cycles. WDT time-out period is 225 clock cycles. WDT time-out period is 222 clock cycles. WDT time-out period is 218 clock cycles.
Note: *RST_FLAG is only cleared by a non-WDT RESET.
Watch-Dog Timer Reset Register The Watch-Dog Timer Reset register, detailed in Table 29, is an 8-bit Write Only register. The Watch-Dog Timer is reset when an A5h value followed by 5Ah is written to this register. Any amount of time can occur between the writing of the A5h value and the 5Ah value, so long as the WDT time-out does not occur prior to completion.
Table 29. Watch-Dog Timer Reset Register (WDT_RR = 0094h) Bit Reset CPU Access 7 X W 6 X W 5 X W 4 X W 3 X W 2 X W 1 X W 0 X W
Note: X = Undefined; W = Write only.
Bit Position [7:0] WDT_RR
Value Description A5h 5Ah The first Write value required to reset the WDT prior to a timeout. The second Write value required to reset the WDT prior to a time-out. If an A5h, 5Ah sequence is written to WDT_RR, the WDT timer is reset to its initial count value, and counting resumes.
PS015309-1004
PRELIMINARY
Watch-Dog Timer
EZ80F92/eZ80F93 Product Specification
77
Programmable Reload Timers
Programmable Reload Timers Overview
The EZ80F92 device features six Programmable Reload Timers (PRT). Each PRT contains a 16-bit downcounter and a 16-bit reload register. In addition, each PRT features a clock divider with four selectable taps for CLK / 4, CLK / 16, CLK / 64, and CLK / 256. Each timer can be individually enabled to operate in either SINGLE PASS or CONTINUOUS mode. The timer can be programmed to start, stop, restart from the current value, or restart from the initial value, and generate interrupts to the CPU. Four of the Programmable Reload Timers (timers 0-3) feature a selectable clock source input. The input for these timers can be either the system clock or the Real-Time Clock (RTC) source. Timers 0-3 can also be used for event counting, with their inputs received from a GPIO port pin. Output from timers 4 and 5 can be directed to a GPIO port pin. Each of the six PRTs available on the EZ80F92 device can be controlled individually. They do not share the same counters, reload registers, control registers, or interrupt signals. A simplified block diagram of a programmable reload timer is illustrated in Figure 20.
Data[7:0]
Data[7:0]
Reload Registers {TMRx_RR_H, TMRx_RR_L}
Control Register TMRx_CTL
System Clock RTC Source GPIO Pin 2 2 Data Registers {TMRx_DR_H, TMRx_DR_L} TOUT_EN (Timers 4-5 only) Adjustable Clock Prescaler 16-Bit Down Counter PRT Control Logic IRQ to eZ80 CPU Timer Out
TMRx_IN TMRx_CTL[3:2] (Timers 0-3 only)
Data[7:0]
Figure 20.Programmable Reload Timer Block Diagram
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Programmable Reload Timers
EZ80F92/eZ80F93 Product Specification
78
Programmable Reload Timer Operation
Setting Timer Duration There are three factors to consider when determining Programmable Reload Timer duration--clock frequency, clock divider ratio, and initial count value. Minimum duration of the timer is achieved by loading 0001h. Maximum duration is achieved by loading 0000h, because the timer first rolls over to FFFFh and then continues counting down to
0000h.
The time-out period of the PRT is returned by the following equation:
PRT Time-Out Period = Clock Divider Ratio x Reload Value System Clock Frequency
To calculate the time-out period with the above equation when using an initial value of 0000h, enter a reload value of 65536 (FFFFh + 1). Minimum time-out duration is 4 times longer than the input clock period and is generated by setting the clock divider ratio to 1:4 and the reload value to 0001h. Maximum time-out duration is 224 (16,777,216) times longer than the input clock period and is generated by setting the clock divider ratio to 1:256 and the reload value to 0000h. Single Pass Mode In SINGLE PASS mode, when the end-of-count value, 0000h, is reached, counting halts, the timer is disabled, and the PRT_EN bit resets to 0. To restart the timer, the CPU must reenable the timer by setting the PRT_EN bit to 1 in the Timer Control Register. To set the downcounter to the value in the reload registers, the RST_EN bit must be set to 1 in the Timer Control Register. An example of a PRT operating in SINGLE PASS mode is illustrated in Figure 21. Timer register information is indicated in Table 30.
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Programmable Reload Timers
EZ80F92/eZ80F93 Product Specification
79
CLK CLKEN IOWRN
t CNTH [7:0] t CNTL [7:0] IRQ 0 4 3
0 2 1 0
Figure 21.PRT SINGLE PASS Mode Operation Example
Table 30. PRT SINGLE PASS Mode Operation Example Parameter PRT Enabled Reload and Restart Enabled PRT Clock Divider = 4 SINGLE PASS Mode PRT Interrupt Enabled PRT Reload Value Control Register(s) TMRx_CTL[0] TMRx_CTL[1] TMRx_CTL[3:2] TMRx_CTL[4] TMRx_CTL[6] {TMRx_RR_H, TMRx_RR_L} Value 1 1 00b 0 1 0004h
Continuous Mode In CONTINUOUS mode, when the end-of-count value, 0000h, is reached, the timer automatically reloads the 16-bit start value from the Timer Reload registers, TMRx_RR_H and TMRx_RR_L. Downcounting continues on the next clock edge. In CONTINUOUS mode, the PRT continues to count until disabled. An example of a PRT operating in CONTINUOUS mode is illustrated in Figure 31. Timer register information is indicated in Table 32.
PS015309-1004
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Programmable Reload Timers
EZ80F92/eZ80F93 Product Specification
80
CLK PRT Clock (Clock / 4) IOWRN PRT Count Value Interrupt Request I/O Write to TMRx_CTL Enables PRT X 4 3 2 1 4 3
Table 31. PRT CONTINUOUS Mode Operation Example
Table 32. PRT CONTINUOUS Mode Operation Example Parameter PRT Enabled Reload and Restart Enabled PRT Clock Divider = 4 CONTINUOUS Mode PRT Interrupt Enabled PRT Reload Value Control Register(s) TMRx_CTL[0] TMRx_CTL[1] TMRx_CTL[3:2] TMRx_CTL[4] TMRx_CTL[6] {TMRx_RR_H, TMRx_RR_L} Value 1 1 00b 1 1 0004h
Reading the Current Count Value The CPU is capable of reading the current count value while the timer is running. This Read event does not affect timer operation. The High byte of the current count value is latched during a Read of the Low byte. Timer Interrupts The timer interrupt flag, PRT_IRQ, is set to 1 whenever the timer reaches its end-of-count value, 0000h, in SINGLE PASS mode, or when the timer reloads the start value in CONTINUOUS mode. The interrupt flag is only set when the timer reaches 0000h (or reloads) from 0001h. The timer interrupt flag is not set to 1 when the timer is loaded with the value 0000h, which selects the maximum time-out period. The CPU can be programmed to poll the PRT_IRQ bit for the time-out event. Alternatively, an interrupt service request signal can be sent to the CPU by setting IRQ_EN to 1.
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Programmable Reload Timers
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Then, when the end-of-count value, 0000h, is reached and PRT_IRQ is set to 1, an interrupt service request signal is passed to the CPU. PRT_IRQ is cleared to 0 and the interrupt service request signal is inactivated whenever the CPU reads from the timer control registers, TMRx_CTL. Timer Input Source Selection Timers 0-3 feature programmable input source selection. By default, the input is taken from the EZ80F92 device's system clock. Alternatively, Timers 0-3 can take their input from port input pins PB0 (Timers 0 and 2) or PB1 (Timers 1 and 3). Timers 0-3 can also use the Real-Time Clock source (50, 60, or 32768Hz) as their clock sources. When the timer clock source is the Real-Time Clock signal, the timer decrements on the second rising edge of the system clock following the falling edge of the RTC_XOUT pin. The input source for these timers is set using the Timer Input Source Select register. Event Counter When Timers 0-3 are configured to take their inputs from port input pins PB0 and PB1, they function as event counters. For event counting, the clock divider is bypassed. The PRT counters decrement on every rising edge of the port pin. The port pins must be configured as inputs. Due to the input sampling on the pins, the event input signal frequency is limited to one-half the system clock frequency. Input sampling on the port pins results in the PRT counter being updated on the fifth rising edge of the system clock after the rising edge occurs at the port pin. Timer Output Two of the Programmable Reload Timers (Timers 4 and 5) can be directed to GPIO Port B output pins (PB4 and PB5, respectively). To enable the Timer Out feature, the GPIO port pin must be configured for alternate functions. After reset, the Timer Output feature is disabled by default. The GPIO output pin toggles each time the PRT reaches its end-of-count value. In CONTINUOUS mode operation, the disabling of the Timer Output feature results in a Timer Output signal period that is twice the PRT time-out period. Examples of the Timer Output operation are illustrated in Figure 22 and Table 33. In these examples, the GPIO output is assumed to be Low (0) when the Timer Output function is enabled.
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CLK
PRT Clock (Clock / 4)
IOWRN PRT Count Value Timer Output
I/O Write to TMRx_CTL Enables PRT
X
3
2
1
3
2
1
Figure 22.PRT Timer Output Operation Example Table 33. PRT Timer Out Operation Example Parameter PRT Enabled Reload and Restart Enabled PRT Clock Divider = 4 CONTINUOUS Mode PRT Reload Value Control Register(s) TMRx_CTL[0] TMRx_CTL[1] TMRx_CTL[3:2] TMRx_CTL[4] {TMRx_RR_H, TMRx_RR_L} Value 1 1 00b 1 0003h
Programmable Reload Timer Registers
Each programmable reload timer is controlled using five 8-bit registers. These registers are the Timer Control register, Timer Reload Low Byte register, Timer Reload High Byte register, Timer Data Low Byte register, and Timer Data High Byte register. The Timer Control register can be read or written to. The timer reload registers are Write Only and are located at the same I/O address as the timer data registers, which are Read Only. Timer Control Register The Timer Control register, detailed in Table 34, is used to control operation of the timer, including enabling the timer, selecting the clock divider, enabling the interrupt, selecting between CONTINUOUS and SINGLE PASS modes, and enabling the auto-reload feature.
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Programmable Reload Timers
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83
Table 34. Timer Control Register (TMR0_CTL = 0080h, TMR1_CTL = 0083h, TMR2_CTL = 0086h, TMR3_CTL = 0089h, TMR4_CTL = 008Ch, or TMR5_CTL = 008Fh) Bit Reset CPU Access 7 0 R 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Note: R = Read only; R/W = Read/Write.
Bit Position 7 PRT_IRQ
Value 0 1
Description The timer does not reach its end-of-count value. This bit is reset to 0 every time the TMRx_CTL register is read. The timer reaches its end-of-count value. If IRQ_EN is set to 1, an interrupt signal is sent to the CPU. This bit remains 1 until the TMRx_CTL register is read. Timer interrupt requests are disabled. Timer interrupt requests are enabled. Reserved. The timer operates in SINGLE PASS mode. PRT_EN (bit 0) is reset to 0, and counting stops when the end-of-count value is reached. The timer operates in CONTINUOUS mode. The timer reload value is written to the counter when the end-of-count value is reached. Clock / 4 is the timer input source. Clock / 16 is the timer input source. Clock / 64 is the timer input source. Clock / 256 is the timer input source. The reload and restart function is disabled. The reload and restart function is enabled. When a 1 is written to this bit, the values in the reload registers are loaded into the downcounter when the timer restarts. The programmer must ensure that this bit is set to 1 each time SINGLE-PASS mode is used. The programmable reload timer is disabled. The programmable reload timer is enabled.
6 IRQ_EN 5
0 1 0
4 0 PRT_MODE 1
[3:2] CLK_DIV
00 01 10 11
1 RST_EN
0 1
0 PRT_EN
0 1
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Timer Data Register--Low Byte This Read Only register returns the Low byte of the current count value of the selected timer. The Timer Data Register--Low Byte, detailed in Table 35, can be read while the timer is in operation. Reading the current count value does not affect timer operation. To read the 16-bit data of the current count value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}, first read the Timer Data Register--Low Byte and then read the Timer Data Register-- High Byte. The Timer Data Register--High Byte value is latched when a Read of the Timer Data Register--Low Byte occurs. Note: The Timer Data registers and Timer Reload registers share the same address space.
Table 35. Timer Data Register--Low Byte (TMR0_DR_L = 0081h, TMR1_DR_L = 0084h, TMR2_DR_L = 0087h, TMR3_DR_L = 008Ah, TMR4_DR_L = 008Dh, or TMR5_DR_L = 0090h) Bit Reset CPU Access
Note: R = Read only.
7 0 R
6 0 R
5 0 R
4 0 R
3 0 R
2 0 R
1 0 R
0 0 R
Bit Position [7:0] TMRx_DR_L
Value
Description
00h-FFh These bits represent the Low byte of the 2-byte timer data value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}. Bit 7 is bit 7 of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the 16bit timer data value.
Timer Data Register--High Byte This Read Only register returns the High byte of the current count value of the selected timer. The Timer Data Register--High Byte, detailed in Table 36, can be read while the timer is in operation. Reading the current count value does not affect timer operation. To read the 16-bit data of the current count value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}, first read the Timer Data Register--Low Byte and then read the Timer Data Register-- High Byte. The Timer Data Register--High Byte value is latched when a Read of the Timer Data Register--Low Byte occurs. Note: The timer data registers and timer reload registers share the same address space.
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Table 36. Timer Data Register--High Byte (TMR0_DR_H = 0082h, TMR1_DR_H = 0085h, TMR2_DR_H = 0088h, TMR3_DR_H = 008Bh, TMR4_DR_H = 008Eh, or TMR5_DR_H = 0091h) Bit Reset CPU Access
Note: R = Read only.
7 0 R
6 0 R
5 0 R
4 0 R
3 0 R
2 0 R
1 0 R
0 0 R
Bit Position
Value
Description
[7:0] 00h-FFh These bits represent the High byte of the 2-byte timer data TMRx_DR_H value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}. Bit 7 is bit 15 (msb) of the 16-bit timer data value. Bit 0 is bit 8 of the 16-bit timer data value.
Timer Reload Register--Low Byte The Timer Reload Register--Low Byte, detailed in Table 37, stores the least-significant byte (LSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload value is reloaded into the timer upon end-of-count. When RST_EN (TMRx_CTL[1]) is set to 1 to enable the automatic reload and restart function, the timer reload value is written to the timer on the next rising edge of the clock. Note: The Timer Data registers and Timer Reload registers share the same address space.
Table 37. Timer Reload Register--Low Byte (TMR0_RR_L = 0081h, TMR1_RR_L = 0084h, TMR2_RR_L = 0087h, TMR3_RR_L = 008Ah, TMR4_RR_L = 008Dh, or TMR5_RR_L = 0090h) Bit Reset CPU Access
Note: W = Write only.
7 0 W
6 0 W
5 0 W
4 0 W
3 0 W
2 0 W
1 0 W
0 0 W
Bit Position [7:0] TMRx_RR_L
Value
Description
00h-FFh These bits represent the Low byte of the 2-byte timer reload value, {TMRx_RR_H[7:0], TMRx_RR_L[7:0]}. Bit 7 is bit 7 of the 16-bit timer reload value. Bit 0 is bit 0 (lsb) of the 16-bit timer reload value.
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PRELIMINARY
Programmable Reload Timers
EZ80F92/eZ80F93 Product Specification
86
Timer Reload Register--High Byte The Timer Reload Register--High Byte, detailed in Table 38, stores the most-significant byte (MSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload value is reloaded into the timer upon end-of-count. When RST_EN (TMRx_CTL[1]) is set to 1 to enable the automatic reload and restart function, the timer reload value is written to the timer on the next rising edge of the clock. Note: The Timer Data registers and Timer Reload registers share the same address space.
Table 38. Timer Reload Register--High Byte (TMR0_RR_H = 0082h, TMR1_RR_H = 0085h, TMR2_RR_H = 0088h, TMR3_RR_H = 008Bh, TMR4_RR_H = 008Eh, or TMR5_RR_H = 0091h) Bit Reset CPU Access
Note: W = Write only.
7 0 W
6 0 W
5 0 W
4 0 W
3 0 W
2 0 W
1 0 W
0 0 W
Bit Position [7:0] TMRx_RR_H
Value
Description
00h-FFh These bits represent the High byte of the 2-byte timer reload value, {TMRx_RR_H[7:0], TMRx_RR_L[7:0]}. Bit 7 is bit 15 (msb) of the 16-bit timer reload value. Bit 0 is bit 8 of the 16-bit timer reload value.
Timer Input Source Select Register The Timer Input Source Select register, detailed in Table 39, sets the input source for Programmable Reload Timer 0-3 (TMR0, TMR1, TMR2, TMR3). Event frequency must be less than one-half of the system clock frequency. When configured for event inputs through the port pins, the Timers decrement on the fifth system clock rising edge following the rising edge of the port pin. The timer event input can arrive from the GPIO port, the real-time clock, or the system clock. The value of the clock divider in the Timer Control Register is ignored when the timer event input is either from the GPIO port pin or the realtime clock source.
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Programmable Reload Timers
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87
Table 39. Timer Input Source Select Register (TMR_ISS = 0092h) Bit Reset CPU Access
Note: R/W = Read/Write.
7 0 R/W
6 0 R/W
5 0 R/W
4 0 R/W
3 0 R/W
2 0 R/W
1 0 R/W
0 0 R/W
Bit Position [7:6] TMR3_IN
Value 00 01
Description The timer counts at the system clock divided by the clock divider. The timer event input is the Real-Time Clock source (32 KHz or 50/60 Hz--refer to the Real-Time Clock section on page 88 for details). The timer event input source is the GPIO Port B pin 1. The timer event input source is the GPIO Port B pin 1. The timer counts at the system clock divided by the clock divider. The timer event input is the Real-Time Clock source (32 KHz or 50/60 Hz--refer to the Real-Time Clock section on page 88 for details). The timer event input is the GPIO Port B pin 0. The timer event input is the GPIO Port B pin 0. The timer counts at the system clock divided by the clock divider. The timer event input is the Real-Time Clock source (32 KHz or 50/60 Hz--refer to the Real-Time Clock section on page 88 for details). The timer event input is the GPIO Port B pin 1. The timer event input is the GPIO Port B pin 1. Timer counts at system clock divided by clock divider. Timer event input is Real-Time Clock source (32 KHz or 50/60 Hz--refer to the Real-Time Clock section on page 88 for details). The timer event input is the GPIO Port B pin 0. The timer event input is the GPIO Port B pin 0.
10 11 [5:4] TMR2_IN 00 01
10 11 [3:2] TMR1_IN 00 01
10 11 [1:0] TMR0_IN 00 01
10 11
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Real-Time Clock
Real-Time Clock Overview
The Real-Time Clock (RTC) keeps time by maintaining a count of seconds, minutes, hours, day-of-the-week, day-of-the-month, year, and century. The current time is kept in 24-hour format. The format for all count and alarm registers is selectable between binary and binary-coded-decimal (BCD). The calendar operation maintains the correct day of the month and automatically compensates for leap year. A simplified block diagram of the RTC and the associated on-chip, low-power, 32 KHz oscillator is illustrated in Figure 23. Connections to an external battery supply and 32 KHz crystal network are also demonstrated in Figure 23.
RTC_VDD VDD IRQ
to eZ80 CPU
Battery
Real-Time Clock
ADDR[15:0] DATA[7:0] R1 RTC Clock RTC_XOUT C
System Clock VDD Enab le CLK_SEL (RTC_CTRL[4])
Low-Power 32 KHz Oscillator
32 KH z Crystal
RTC_XIN C
Figure 23.Real-Time Clock and 32KHz Oscillator Block Diagram
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Real-Time Clock Alarm
The clock can be programmed to generate an alarm condition when the current count matches the alarm set-point registers. Alarm registers are available for seconds, minutes, hours, and day-of-the-week. Each alarm can be independently enabled. To generate an alarm condition, the current time must match all enabled alarm values. For example, if the day-of-the-week and hour alarms are both enabled, the alarm only occurs at the specified hour on the specified day. The alarm triggers an interrupt if the interrupt enable bit, INT_EN, is set. The alarm flag, ALARM, and corresponding interrupt to the CPU are cleared by reading the RTC_CTRL register. Alarm value registers and alarm control registers can be written at any time. Alarm conditions are generated when the count value matches the alarm value. The comparison of alarm and count values occurs whenever the RTC count increments (one time every second). The RTC can also be forced to perform a comparison at any time by writing a 0 to the RTC_UNLOCK bit (RTC_UNLOCK is not required to be changed to a 1 first).
Real-Time Clock Oscillator and Source Selection
The RTC count is driven by either an external 32 KHz on-chip oscillator or a 50/60 Hz power-line frequency input connected to the 32 KHz RTC_XOUT pin. An internal divider compensates for each of these options. The clock source and power-line frequencies are selected in the RTC_CTRL register. Writing to the RTC_CTRL register resets the clock divider.
Real-Time Clock Battery Backup
The power supply pin (RTC_VDD) for the Real-Time Clock and associated low-power 32 KHz oscillator is isolated from the other power supply pins on the EZ80F92 device. To ensure that the RTC continues to keep time in the event of loss of line power to the application, a battery can be used to supply power to the RTC and the oscillator via the RTC_VDD pin. All VSS (ground) pins should be connected together on the printed circuit assembly.
Real-Time Clock Recommended Operation
Following a RESET from a powered-down condition, the counter values of the RTC are undefined and all alarms are disabled. After a RESET from a powered-down condition, the following procedure is recommended:
* * *
PS015309-1004
Write to RTC_CTRL to set RTC_UNLOCK and CLK_SEL Write values to the RTC count registers to set the current time Write values to the RTC alarm registers to set the appropriate alarm conditions
PRELIMINARY
Real-Time Clock
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*
Write to RTC_CTRL to clear the RTC_UNLOCK bit; clearing the RTC_UNLOCK bit resets and enables the clock divider
Real-Time Clock Registers
The Real-Time Clock registers are accessed via the address and data bus using I/O instructions. RTC_UNLOCK controls access to the RTC count registers. When unlocked (RTC_UNLOCK = 1), the RTC count is disabled and the count registers are Read/Write. When locked (RTC_UNLOCK = 0), the RTC count is enabled and the count registers are Read Only. The default, at RESET, is for the RTC to be locked. Real-Time Clock Seconds Register This register contains the current seconds count. The value in the RTC_SEC register is unchanged by a RESET. The current setting of BCD_EN determines whether the values in this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). Access to this register is Read Only if the RTC is locked and Read/Write if the RTC is unlocked. See Table 40.
Table 40. Real-Time Clock Seconds Register (RTC_SEC = 00E0h) Bit Reset CPU Access 7 X R/W* 6 X R/W* 5 X R/W* 4 X R/W* 3 X R/W* 2 X R/W* 1 X R/W* 0 X R/W*
Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1) Bit Position [7:4] TEN_SEC [3:0] SEC Value Description 0-5 0-9 The tens digit of the current seconds count. The ones digit of the current seconds count.
Binary Operation (BCD_EN = 0) Bit Position [7:0] SEC Value Description 00h- 3Bh The current seconds count.
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91
Real-Time Clock Minutes Register This register contains the current minutes count. See Table 41.
Table 41. Real-Time Clock Minutes Register (RTC_MIN = 00E1h) Bit Reset CPU Access 7 X R/W* 6 X R/W* 5 X R/W* 4 X R/W* 3 X R/W* 2 X R/W* 1 X R/W* 0 X R/W*
Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1) Bit Position [7:4] TEN_MIN [3:0] MIN Value Description 0-5 0-9 The tens digit of the current minutes count. The ones digit of the current minutes count.
Binary Operation (BCD_EN = 0) Bit Position [7:0] MIN Value Description 00h- 3Bh The current minutes count.
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Real-Time Clock Hours Register This register contains the current hours count. See Table 42.
Table 42. Real-Time Clock Hours Register (RTC_HRS = 00E2h) Bit Reset CPU Access 7 X R/W* 6 X R/W* 5 X R/W* 4 X R/W* 3 X R/W* 2 X R/W* 1 X R/W* 0 X R/W*
Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1) Bit Position [7:4] TEN_HRS [3:0] HRS Value Description 0-2 0-9 The tens digit of the current hours count. The ones digit of the current hours count.
Binary Operation (BCD_EN = 0) Bit Position [7:0] HRS Value Description 00h- 17h The current hours count.
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Real-Time Clock Day-of-the-Week Register This register contains the current day-of-the-week count. The RTC_DOW register begins counting at 01h. See Table 43.
Table 43. Real-Time Clock Day-of-the-Week Register (RTC_DOW = 00E3h) Bit Reset CPU Access 7 0 R 6 0 R 5 0 R 4 0 R 3 X R/W* 2 X R/W* 1 X R/W* 0 X R/W*
Note: X = Unchanged by RESET; R = Read Only; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1) Bit Position [7:4] [3:0] DOW Value Description 0000 1-7 Reserved. The current day-of-the-week.count.
Binary Operation (BCD_EN = 0) Bit Position [7:4] [3:0] DOW Value Description 0000 01h- 07h Reserved. The current day-of-the-week count.
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Real-Time Clock Day-of-the-Month Register This register contains the current day-of-the-month count. The RTC_DOM register begins counting at 01h. See Table 44.
Table 44. Real-Time Clock Day-of-the-Month Register (RTC_DOM = 00E4h) Bit Reset CPU Access 7 X R/W* 6 X R/W* 5 X R/W* 4 X R/W* 3 X R/W* 2 X R/W* 1 X R/W* 0 X R/W*
Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1) Bit Position [7:4] TENS_DOM [3:0] DOM Value Description 0-3 0-9 The tens digit of the current day-of-the-month count. The ones digit of the current day-of-the-month count.
Binary Operation (BCD_EN = 0) Bit Position [7:0] DOM Value Description 01h- 1Fh The current day-of-the-month count.
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Real-Time Clock Month Register This register contains the current month count. See Table 45.
Table 45. Real-Time Clock Month Register (RTC_MON = 00E5h) Bit Reset CPU Access 7 X R/W* 6 X R/W* 5 X R/W* 4 X R/W* 3 X R/W* 2 X R/W* 1 X R/W* 0 X R/W*
Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1) Bit Position [7:4] TENS_MON [3:0] MON Value Description 0-1 0-9 The tens digit of the current month count. The ones digit of the current month count.
Binary Operation (BCD_EN = 0) Bit Position [7:0] MON Value Description 01h- 0Ch The current month count.
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Real-Time Clock Year Register This register contains the current year count. See Table 46.
Table 46. Real-Time Clock Year Register (RTC_YR = 00E6h) Bit Reset CPU Access 7 X R/W* 6 X R/W* 5 X R/W* 4 X R/W* 3 X R/W* 2 X R/W* 1 X R/W* 0 X R/W*
Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1) Bit Position [7:4] TENS_YR [3:0] YR Value Description 0-9 0-9 The tens digit of the current year count. The ones digit of the current year count.
Binary Operation (BCD_EN = 0) Bit Position [7:0] YR Value Description 00h- 63h The current year count.
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Real-Time Clock Century Register This register contains the current century count. See Table 47.
Table 47. Real-Time Clock Century Register (RTC_CEN = 00E7h) Bit Reset CPU Access 7 X R/W* 6 X R/W* 5 X R/W* 4 X R/W* 3 X R/W* 2 X R/W* 1 X R/W* 0 X R/W*
Note: X = Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1) Bit Position [7:4] TENS_CEN [3:0] CEN Value Description 0-9 0-9 The tens digit of the current century count. The ones digit of the current century count.
Binary Operation (BCD_EN = 0) Bit Position [7:0] CEN Value Description 00h- 63h The current century count.
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Real-Time Clock Alarm Seconds Register This register contains the alarm seconds value. See Table 48.
Table 48. Real-Time Clock Alarm Seconds Register (RTC_ASEC = 00E8h) Bit Reset CPU Access 7 X R/W 6 X R/W 5 X R/W 4 X R/W 3 X R/W 2 X R/W 1 X R/W 0 X R/W
Note: X = Unchanged by RESET; R/W = Read/Write.
Binary-Coded-Decimal Operation (BCD_EN = 1) Bit Position [7:4] ATEN_SEC [3:0] ASEC Value Description 0-5 0-9 The tens digit of the alarm seconds value. The ones digit of the alarm seconds value.
Binary Operation (BCD_EN = 0) Bit Position [7:0] ASEC Value Description 00h- 3Bh The alarm seconds value.
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Real-Time Clock Alarm Minutes Register This register contains the alarm minutes value. See Table 49.
Table 49. Real-Time Clock Alarm Minutes Register (RTC_AMIN = 00E9h) Bit Reset CPU Access 7 X R/W 6 X R/W 5 X R/W 4 X R/W 3 X R/W 2 X R/W 1 X R/W 0 X R/W
Note: X = Unchanged by RESET; R/W = Read/Write.
Binary-Coded-Decimal Operation (BCD_EN = 1) Bit Position [7:4] ATEN_MIN [3:0] AMIN Value Description 0-5 0-9 The tens digit of the alarm minutes value. The ones digit of the alarm minutes value.
Binary Operation (BCD_EN = 0) Bit Position [7:0] AMIN Value Description 00h- 3Bh The alarm minutes value.
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Real-Time Clock Alarm Hours Register This register contains the alarm hours value. See Table 50.
Table 50. Real-Time Clock Alarm Hours Register (RTC_AHRS = 00EAh) Bit Reset CPU Access 7 X R/W 6 X R/W 5 X R/W 4 X R/W 3 X R/W 2 X R/W 1 X R/W 0 X R/W
Note: X = Unchanged by RESET; R/W = Read/Write.
Binary-Coded-Decimal Operation (BCD_EN = 1) Bit Position [7:4] ATEN_HRS [3:0] AHRS Value Description 0-2 0-9 The tens digit of the alarm hours value. The ones digit of the alarm hours value.
Binary Operation (BCD_EN = 0) Bit Position [7:0] AHRS Value Description 00h- 17h The alarm hours value.
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Real-Time Clock Alarm Day-of-the-Week Register This register contains the alarm day-of-the-week value. See Table 51.
Table 51. Real-Time Clock Alarm Day-of-the-Week Register (RTC_ADOW = 00EBh) Bit Reset CPU Access 7 0 R 6 0 R 5 0 R 4 0 R 3 X R/W* 2 X R/W* 1 X R/W* 0 X R/W*
Note: X = Unchanged by RESET; R = Read Only; R/W* = Read Only if RTC locked, Read/Write if RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1) Bit Position [7:4] [3:0] ADOW Value Description 0000 1-7 Reserved. The alarm day-of-the-week.value.
Binary Operation (BCD_EN = 0) Bit Position [7:4] [3:0] ADOW Value Description 0000 01h- 07h Reserved. The alarm day-of-the-week value.
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Real-Time Clock Alarm Control Register This register contains alarm enable bits for the Real-Time Clock. The RTC_ACTRL register is cleared by a RESET. See Table 52.
Table 52. Real-Time Clock Alarm Control Register (RTC_ACTRL = 00ECh) Bit Reset CPU Access 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Note: X = Unchanged by RESET; R/W = Read/Write; R = Read Only.
Bit Position [7:4] 3 ADOW_EN 2 AHRS_EN 1 AMIN_EN 0 ASEC_EN
Value Description 0000 0 1 0 1 0 1 0 1 Reserved. The day-of-the-week alarm is disabled. The day-of-the-week alarm is enabled. The hours alarm is disabled. The hours alarm is enabled. The minutes alarm is disabled. The minutes alarm is enabled. The seconds alarm is disabled. The seconds alarm is enabled.
Real-Time Clock Control Register This register contains control and status bits for the Real-Time Clock. Some bits in the RTC_CTRL register are cleared by a RESET. The ALARM flag and associated interrupt (if INT_EN is enabled) are cleared by reading this register. The ALARM flag is updated by clearing (locking) the RTC_UNLOCK bit or by an increment of the RTC count. Writing to the RTC_CTRL register also resets the RTC clock divider allowing the RTC to be synchronized to another time source. SLP_WAKE indicates if an RTC alarm condition initiated the CPU recovery from SLEEP mode. This bit can be checked after RESET to determine if a sleep-mode recovery is caused by the RTC. SLP_WAKE is cleared by a Read of the RTC_CTRL register. Setting BCD_EN causes the RTC to use BCD counting in all registers including the alarm set points. CLK_SEL and FREQ_SEL select the RTC clock source. If the 32 KHz crystal option is selected the oscillator is enabled and the internal clock divider is set to divide by 32768. If
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the power-line frequency option is selected, the prescale value is set by FREQ_SEL, and the 32 Khz oscillator is disabled. See Table 53.
Table 53. Real-Time Clock Control Register (RTC_CTRL = 00EDh) Bit Reset CPU Access 7 X R 6 0 R/W 5 X R/W 4 X R/W 3 X R/W 2 X R 1 0/1 R 0 0 R/W
Note: X = Unchanged by RESET; R = Read Only; R/W = Read/Write.
Bit Position 7 ALARM 6 INT_EN 5 BCD_EN
Value Description 0 1 0 1 0 1 0 1 Alarm interrupt is inactive. Alarm interrupt is active. Interrupt on alarm condition is disabled. Interrupt on alarm condition is enabled. RTC count and alarm value registers are binary. RTC count and alarm value registers are binary-coded decimal (BCD). RTC clock source is crystal oscillator output (32768 Hz). On-chip 32768Hz oscillator is enabled. RTC clock source is power-line frequency input. On-chip 32768 Hz oscillator is disabled. Power-line frequency is 60 Hz. Power-line frequency is 50 Hz. Reserved. RTC does not generate a sleep-mode recovery reset. RTC Alarm generates a sleep-mode recovery reset. RTC count registers are locked to prevent Write access. RTC counter is enabled. RTC count registers are unlocked to allow Write access. RTC counter is disabled.
4 CLK_SEL
3 FREQ_SEL 2 1 SLP_WAKE
0 1 0 0 1
0 0 RTC_UNLOCK 1
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Universal Asynchronous Receiver/Transmitter
The UART module implements all of the logic required to support several asynchronous communications protocols. The module also implements two separate 16-byte-deep FIFOs for both transmission and reception. A block diagram of the UART is illustrated in Figure 24.
System Clock
to eZ80 CPU
UART Control Interface and Baud Rate Generator
Receive Buffer
RxD0/RxD1
I/O Address Data Interrupt Signal
Transmit Buffer
TxD0/TxD1
Modem Control Logic
CTS0/CTS1 RTS0/RTS1 DSR0/DSR1 DTR0/DTR1 DCD0/DCD1 RI0/RI1
Figure 24.UART Block Diagram
The UART module provides the following asynchronous communication protocol-related features and functions:
* * * * * * *
5-, 6-, 7-, 8- or 9-bit data transmission Even/odd, space/mark, or no parity bit generation and detection Start and stop bit generation and detection supports up to two stop bits) Line break detection and generation Receiver overrun and framing errors detection Logic and associated I/O to provide modem handshake capability
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UART Functional Description
The UART function implements:
* * *
The transmitter and associated control logic The receiver and associated control logic The modem interface and associated logic
UART Functions
The UART function implements:
* * *
The transmitter and associated control logic The receiver and associated control logic The modem interface and associated logic
UART Transmitter The transmitter block controls the data transmitted on the TxD output. It implements the FIFO, accessed through the UARTx_THR register, the transmit shift register, the parity generator, and control logic for the transmitter to control parameters for the asynchronous communication protocol. The UARTx_THR is a Write Only register. The processor writes the data byte to be transmitted into this register. In the FIFO mode, up to 16 data bytes can be written via the UARTx_THR register. The data byte from the FIFO is transferred to the transmit shift register at the appropriate time and transmitted out on TxD output. After SYNC_RESET, the UARTx_THR register is empty. Therefore, the Transmit Holding Register Empty (THRE) bit (bit 5 of the UARTx_LSR register) is 1 and an interrupt is sent to the processor (if interrupts are enabled). The processor can reset this interrupt by loading data into the UARTx_THR register, which clears the transmitter interrupt. The transmit shift register places the byte to be transmitted on the TxD signal serially. The least-significant bit of the byte to be transmitted is shifted out first and the most-significant bit is shifted out last. The control logic within the block adds the asynchronous communication protocol bits to the data byte being transmitted. The transmitter block obtains the parameters for the protocol from the bits programmed via the UARTx_LCTL register. When enabled, an interrupt is generated after the most recent protocol bit is transmitted, which the processor may reset by loading data into the UARTx_THR register. The TxD output is set to 1 if the transmitter is idle (it does not contain any data to be transmitted). The transmitter operates with the Baud Rate Generator (BRG) clock. The data bits are placed on the TxD output one time every 16 BRG clock cycles. The transmitter block also implements a parity generator that attaches the parity bit to the byte, if programmed. For
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9-bit data, the host processor programs the parity bit generator so that it marks the byte as either address (mark parity) or data (space parity). UART Receiver The receiver block controls the data reception from the RxD signal. The receiver block implements a receiver shift register, receiver line error condition monitoring logic and Receiver Data Ready logic. It also implements the parity checker. The UARTx_RBR is a Read Only register of the module. The processor reads received data from this register. The condition of the UARTx_RBR register is monitored by the DR bit (bit 0 of the UARTx_LSR register). The DR bit is 1 when a data byte is received and transferred to the UARTx_RBR register from the receiver shift register. The DR bit is reset only when the processor reads all of the received data bytes. If the number of bits received is less than eight, the unused most-significant bits of the data byte Read are 0 For 9-bit data, the receiver checks incoming bytes for space parity. This check routine generates a line status interrupt when an address byte is received, because address bytes contain mark parity bits. The processor clears the interrupt, determines if the address matches its own, then configures the receiver to either accept the subsequent data bytes if the address matches, or ignore the data if it does not. The receiver uses the clock from the BRG for receiving the data. This clock must be 16 times the appropriate baud rate. The receiver synchronizes the shift clock on the falling edge of the RxD input start bit. It then receives a complete byte according to the set parameters. The receiver also implements logic to detect framing errors, parity errors, overrun errors, and break signals. UART Modem Control The modem control logic provides two outputs and four inputs for handshaking with the modem. Any change in the modem status inputs, except RI, is detected and an interrupt can be generated. For RI, an interrupt is generated only when the trailing edge of the RI is detected. The module also provides LOOP mode for self-diagnostics.
UART Interrupts
There are six different sources of interrupts from the UART. The six sources of interrupts are:
* * *
Transmitter (two different interrupts) Receiver (three different interrupts) Modem status
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UART Transmitter Interrupt The transmitter hold register empty interrupt is generated if there is no data available in the hold register. The transmission complete interrupt is generated after the data in the shift register is sent. Both interrupts can be disabled using individual interrupt enable bits or cleared by writing data into the UARTx_THR register. UART Receiver Interrupts A receiver interrupt can be generated by three possible sources. The first source, a Receiver Data Ready, indicates that one or more data bytes are received and are ready to be read. This interrupt is generated if the number of bytes in the receiver FIFO is greater than or equal to the trigger level. If the FIFO is not enabled, the interrupt is generated if the receive buffer contains a data byte. This interrupt is cleared by reading the UARTx_RBR. The second interrupt source is the receiver time-out. A receiver time-out interrupt is generated when there are fewer data bytes in the receiver FIFO than the trigger level and there are no reads and writes to or from the receiver FIFO for four consecutive byte times. When the receiver time-out interrupt is generated, it is cleared only after emptying the entire receive FIFO. The first two interrupt sources from the receiver (data ready and time-out) share an interrupt enable bit. The third source of a receiver interrupt is a line status error, indicating an error in byte reception. This error may result from:
* * * *
Incorrect received parity. For 9-bit data, incorrect parity indicates detection of an address byte Incorrect framing; that is, the stop bit is not detected by receiver at the end of the byte Receiver over run condition A BREAK condition being detected on the receive data input
An interrupt due to one of the above conditions is cleared when the UARTx_LSR register is read. In FIFO mode, a line status interrupt is generated only after the received byte with an error reaches the top of the FIFO and is ready to be read. A line status interrupt is activated (provided this interrupt is enabled) as long as the Read pointer of the receiver FIFO points to the location of the FIFO that contains a byte with the error. The interrupt is immediately cleared when the UARTx_LSR register is read. The ERR bit of the UARTx_LSR register is active as long as an erroneous byte is present in the receiver FIFO. UART Modem Status Interrupt The modem status interrupt is generated if there is any change in state of the modem status inputs to the UART. This interrupt is cleared when the processor reads the UARTx_MSR register.
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UART Recommended Usage
The following is the standard sequence of events that occur in the EZ80F92 device using the UART. A description of each follows.
* * *
Module reset Control transfers to configure UART operation Data transfers
Module Reset Upon reset, all internal registers are set to their default values. All command status registers are programmed with their default values, and the FIFOs are flushed. Control Transfers Based on the requirements of the application, the data transfer baud rate is determined and the BRG is configured to generate a 16X clock frequency. Interrupts are disabled and the communication control parameters are programmed in the UARTx_LCTL register. The FIFO configuration is determined and the receive trigger levels are set in the UARTx_FCTL register. The status registers, UARTx_LSR and UARTx_MSR, are read, and ensure that none of the interrupt sources are active. The interrupts are enabled (except for the transmit interrupt) and the application is ready to use the module for transmission/ reception. Data Transfers
Transmit. To transmit data, the application enables the transmit interrupt. An interrupt is
immediately expected in response. The application reads the UARTx_IIR register and determines whether the interrupt occurs due to an empty UARTx_THR register or due to a completed transmission. Upon this determination, the application writes the pertinent transmit data bytes to the UARTx_THR register. The number of bytes that the application writes depends on whether or not the FIFO is enabled. If the FIFO is enabled, the application can write 16 bytes at a time. If not, the application can write one byte at a time. As a result of the first Write, the interrupt is deactivated. The processor then waits for the next interrupt. When the interrupt is raised by the UART module, the processor repeats the same process until it exhausts all of the data for transmission. To control and check the modem status, the application sets up the modem by writing to the UARTx_MCTL register and reading the UARTx_MCTL register before starting the process mentioned above.
Receive. The receiver is always enabled, and it continually checks for the start bit on the
RxD input signal. When an interrupt is raised by the UART module, the application reads the UARTx_IIR register and determines the cause for the interrupt. If the cause is a line status interrupt, the application reads the UARTx_LSR register, reads the data byte and
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then can discard the byte or take other appropriate action. If the interrupt is caused by a receive-data-ready condition, the application alternately reads the UARTx_LSR and UARTx_RBR registers and removes all of the received data bytes. It reads the UARTx_LSR register before reading the UARTx_RBR register to determine that there is no error in the received data. To control and check modem status, the application sets up the modem by writing to the UARTx_MCTL register and reading the UARTx_MSR register before starting the process mentioned above.
Poll Mode Transfers. When interrupts are disabled, all data transfers are referred to as
poll mode transfers. In poll mode transfers, the application must continually poll the UARTx_LSR register to transmit or receive data without enabling the interrupts. The same is true for the UARTx_MSR register. If the interrupts are not enabled, the data in the UARTx_IIR register cannot be used to determine the cause of an interrupt.
Baud Rate Generator
The Baud Rate Generator consists of a 16-bit downcounter, two registers, and associated decoding logic. The initial value of the Baud Rate Generator is defined by the two BRG Divisor Latch registers, {UARTx_BRG_H, UARTx_BRG_L}. At the rising edge of each system clock, the BRG decrements until it reaches the value 0001h. On the next system clock rising edge, the BRG reloads the initial value from {UARTx_BRG_H, UARTx_BRG_L) and outputs a pulse to indicate the end-of-count. Calculate the UART data rate with the following equation:
UART Data Rate (bits/s) = System Clock Frequency 16 X (UART Baud Rate Generator Divisor)
Upon RESET, the 16-bit BRG divisor value resets to 0002h. A minimum BRG divisor value of 0001h is also valid, and effectively bypasses the BRG. A software Write to either the Low- or High-byte registers for the BRG Divisor Latch causes both the Low and High bytes to load into the BRG counter, and causes the count to restart. The divisor registers can only be accessed if bit 7 of the UART Line Control register (UARTx_LCTL) is set to 1. After reset, this bit is reset to 0. Recommended Usage of the Baud Rate Generator The following is the normal sequence of operations that should occur after the EZ80F92 device is powered on to configure the Baud Rate Generator:
* *
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* *
Program the UARTx_BRG_L and UARTx_BRG_H registers Clear UARTx_LCTL[7] to 0 to disable access of the BRG divisor registers
BRG Control Registers
UART Baud Rate Generator Register--Low and High Bytes The registers hold the Low and High bytes of the 16-bit divisor count loaded by the processor for UART baud rate generation. The 16-bit clock divisor value is returned by {UARTx_BRG_H, UARTx_BRG_L}, where x is either 0 or 1 to identify the two available UART devices. Upon RESET, the 16-bit BRG divisor value resets to 0002h. The initial 16-bit divisor value must be between 0002h and FFFFh as the values 0000h and 0001h are invalid, and proper operation is not guaranteed. As a result, the minimum BRG clock divisor ratio is 2. A Write to either the Low- or High-byte registers for the BRG Divisor Latch causes both bytes to be loaded into the BRG counter. The count is then restarted. Bit 7 of the associated UART Line Control register (UARTx_LCTL) must be set to 1 to access this register. See Tables 54 and 55. Refer to the UART Line Control Register (UARTx_LCTL) on page 116 for more information. Note: The UARTx_BRG_L registers share the same address space with the UARTx_RBR and UARTx_THR registers. The UARTx_BRG_H registers share the same address space with the UARTx_IER registers. Bit 7 of the associated UART Line Control register (UARTx_LCTL) must be set to 1 to enable access to the BRG registers.
Table 54. UART Baud Rate Generator Register--Low Bytes (UART0_BRG_L = 00C0h, UART1_BRG_L = 00D0h) Bit Reset CPU Access 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 1 R/W 0 0 R/W
Note: R = Read only; R/W = Read/Write.
Bit Position [7:0] UART_BRG_L
Value 00h- FFh
Description These bits represent the Low byte of the 16-bit Baud Rate Generator divider value. The complete BRG divisor value is returned by {UART_BRG_H, UART_BRG_L}.
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Table 55. UART Baud Rate Generator Register--High Bytes (UART0_BRG_H = 00C1h, UART1_BRG_H = 00D1h) Bit Reset CPU Access 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Note: R = Read only; R/W = Read/Write.
Bit Position [7:0] UART_BRG_H
Value 00h- FFh
Description These bits represent the High byte of the 16-bit Baud Rate Generator divider value. The complete BRG divisor value is returned by {UART_BRG_H, UART_BRG_L}.
UART Registers
After a RESET, all UART registers are set to their default values. Any writes to unused registers or register bits are ignored and reads return a value of 0. For compatibility with future revisions, unused bits within a register should always be written with a value of 0. Read/Write attributes, reset conditions, and bit descriptions of all of the UART registers are provided in this section. UART Transmit Holding Register If less than eight bits are programmed for transmission, the lower bits of the byte written to this register are selected for transmission. The transmit FIFO is mapped at this address. The user can write up to 16 bytes for transmission at one time to this address if the FIFO is enabled by the application. If the FIFO is disabled, this buffer is only one byte deep. These registers share the same address space as the UARTx_RBR and UARTx_BRG_L registers. See Table 56.
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Table 56. UART Transmit Holding Registers (UART0_THR = 00C0h, UART1_THR = 00D0h) Bit Reset CPU Access
Note: W = Write only.
7 X W
6 X W
5 X W
4 X W
3 X W
2 X W
1 X W
0 X W
Bit Position [7:0]
Value 00h- FFh
Description Transmit data byte.
TxD
UART Receive Buffer Register The bits in this register reflect the data received. If less than eight bits are programmed for receive, the lower bits of the byte reflect the bits received whereas upper unused bits are 0. The receive FIFO is mapped at this address. If the FIFO is disabled, this buffer is only one byte deep. These registers share the same address space as the UARTx_THR and UARTx_BRG_L registers. See Table 57.
Table 57. UART Receive Buffer Registers (UART0_RBR = 00C0h, UART1_RBR = 00 D0h) Bit Reset CPU Access
Note: R = Read only.
7 X R
6 X R
5 X R
4 X R
3 X R
2 X R
1 X R
0 X R
Bit Position [7:0]
Value 00h- FFh
Description Receive data byte.
RxD
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UART Interrupt Enable Register The UARTx_IER register is used to enable and disable the UART interrupts. The UARTx_IER registers share the same I/O addresses as the UARTx_BRG_H registers. See Table 58.
Table 58. UART Interrupt Enable Registers (UART0_IER = 00C1h, UART1_IER = 00D1h) Bit Reset CPU Access 7 0 R 6 0 R 5 0 R 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Note: R = Read Only; R/W = Read/Write.
Bit Position [7:5] 4 TCIE
Value 000 0 1 0 1 0 1
Description Reserved. Transmission complete interrupt is disabled. Transmission complete interrupt is generated when both the transmit hold register and the transmit shift register are empty. Modem interrupt on edge detect of status inputs is disabled. Modem interrupt on edge detect of status inputs is enabled. Line status interrupt is disabled. Line status interrupt is enabled for receive data errors: incorrect parity bit received, framing error, overrun error, or break detection. Transmit interrupt is disabled. Transmit interrupt is enabled. Interrupt is generated when the transmit FIFO/buffer is empty indicating no more bytes available for transmission. Receive interrupt is disabled. Receive interrupt and receiver time-out interrupt are enabled. Interrupt is generated if the FIFO/buffer contains data ready to be read or if the receiver times out.
3 MIIE 2 LSIE
1 TIE
0 1
0 RIE
0 1
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UART Interrupt Identification Register The Read Only UARTx_IIR register allows the user to check whether the FIFO is enabled and the status of interrupts. These registers share the same I/O addresses as the UARTx_FCTL registers. See Tables 59 and 60.
Table 59. UART Interrupt Identification Registers (UART0_IIR = 00C2h, UART1_IIR = 00D2h) Bit Reset CPU Access
Note: R = Read only.
7 0 R
6 0 R
5 0 R
4 0 R
3 0 R
2 0 R
1 0 R
0 1 R
Bit Position [7:6] FSTS
Value 00 10 11
Description FIFO is disabled. Receive FIFO is disabled (MULTIDROP mode). FIFO is enabled. Reserved. Interrupt Status Code The code indicated in these three bits is valid only if INTBIT is 1. If two internal interrupt sources are active and their respective enable bits are High, only the higher priority interrupt is seen by the application. The lower-priority interrupt code is indicated only after the higher-priority interrupt is serviced. Table 60 lists the interrupt status codes. There is an active interrupt source within the UART. There is not an active interrupt source within the UART.
[5:4] [3:1] INSTS
00 000- 110
0 INTBIT
0 1
Table 60. UART Interrupt Status Codes INSTS Value 011 010 110 101
Priority Highest Second Third Fourth
Interrupt Type Receiver Line Status Receiver Data Ready or Trigger Level Character Time-out Transmission Complete
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Table 60. UART Interrupt Status Codes (Continued) INSTS Value 001 000
Priority Fifth Lowest
Interrupt Type Transmit Buffer Empty Modem Status
UART FIFO Control Register This register is used to monitor trigger levels, clear FIFO pointers, and enable or disable the FIFO. The UARTx_FCTL registers share the same I/O addresses as the UARTx_IIR registers. See Table 61.
Table 61. UART FIFO Control Registers (UART0_FCTL = 00C2h, UART1_FCTL = 00D2h) Bit Reset CPU Access
Note: W = Write only.
7 0 W
6 0 W
5 0 W
4 0 W
3 0 W
2 0 W
1 0 W
0 0 W
Bit Position [7:6] TRIG
Value 00
Description Receive FIFO trigger level set to 1. Receive data interrupt is generated when there is 1 byte in the FIFO. Valid only if FIFO is enabled. Receive FIFO trigger level set to 4. Receive data interrupt is generated when there are 4 bytes in the FIFO. Valid only if FIFO is enabled. Receive FIFO trigger level set to 8. Receive data interrupt is generated when there are 8 bytes in the FIFO. Valid only if FIFO is enabled. Receive FIFO trigger level set to 14. Receive data interrupt is generated when there are 14 bytes in the FIFO. Valid only if FIFO is enabled. Reserved. No effect. Clear the transmit FIFO and reset the transmit FIFO pointer. Valid only if the FIFO is enabled.
01
10
11
[5:3] 2 CLRTXF
000 0 1
Note: *Receive FIFO is not enabled during MULTIDROP mode.
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Bit Position 1 CLRRXF
Value 0 1
Description No effect. Clear the receive FIFO, clear the receive error FIFO, and reset the receive FIFO pointer. Valid only if the FIFO is enabled. Transmit and receive FIFOs are disabled. Transmit and receive buffers are only 1 byte deep. Transmit and receive FIFOs are enabled*.
0 FIFOEN
0 1
Note: *Receive FIFO is not enabled during MULTIDROP mode.
UART Line Control Register This register is used to control the communication control parameters. See Tables 62 and 63.
Table 62. UART Line Control Registers (UART0_LCTL = 00C3h, UART1_LCTL = 00D3h) Bit Reset CPU Access
Note: R/W = Read/Write.
7 0 R/W
6 0 R/W
5 0 R/W
4 0 R/W
3 0 R/W
2 0 R/W
1 0 R/W
0 0 R/W
Bit Position 7 DLAB
Value 0 1
Description Access to the UART registers at I/O addresses UARTx_RBR, UARTx_THR, and UARTx_IER is enabled. Access to the Baud Rate Generator registers at I/O addresses UARTx_BRG_L and UARTx_BRG_H is enabled.
Note: *Receive Parity is set to SPACE in MULTIDROP mode.
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Bit Position 6 SB
Value 0 1
Description Do not send a BREAK signal. Send Break UART sends continuous zeroes on the transmit output from the next bit boundary. The transmit data in the transmit shift register is ignored. After forcing this bit High, the TxD output is 0 only after the bit boundary is reached. Just before forcing TxD to 0, the transmit FIFO is cleared. Any new data written to the transmit FIFO during a break should be written only after the THRE bit of UARTx_LSR register goes High. This new data is transmitted after the UART recovers from the break. After the break is removed, the UART recovers from the break for the next BRG edge. Do not force a parity error. Force a parity error. When this bit and the party enable bit (PEN) are both 1, an incorrect parity bit is transmitted with the data byte. Use odd parity for transmit and receive. The total number of 1 bits in the transmit data plus parity bit is odd. Use as a SPACE bit in MULTIDROP mode. See Table 64 for parity select definitions.* Use even parity for transmit and receive. The total number of 1 bits in the transmit data plus parity bit is even. Use as a MARK bit in MULTIDROP mode. See Table 64 for parity select definitions. Parity bit transmit and receive is disabled. Parity bit transmit and receive is enabled. For transmit, a parity bit is generated and transmitted with every data character. For receive, the parity is checked for every incoming data character. In MULTIDROP mode, receive parity is checked for space parity. UART Character Parameter Selection--see Table 63 for a description of the values.
5 FPE
0 1
4 EPS
0
1
3 PEN
0 1
[2:0] CHAR
000- 111
Note: *Receive Parity is set to SPACE in MULTIDROP mode.
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Table 63. UART Character Parameter Definition Character Length (Tx/Rx Data Bits) 5 6 7 8 5 6 7 8 Stop Bits (Tx Stop Bits) 1 1 1 1 2 2 2 2
CHAR[2:0] 000 001 010 011 100 101 110 111
Table 64. Parity Select Definition for Multidrop Communications MDM UARTx_MGTL[5] 0 0 1 1 EPS UARTx_LCTL940 0 1 0 1*
Parity Type odd even space mark
Note: *In MULTIDROP mode, EPS resets to 0 after the first character is sent.
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UART Modem Control Register This register is used to control and check the modem status, as detailed in Table 65.
Table 65. UART Modem Control Registers (UART0_MCTL = 00C4h, UART1_MCTL = 00D4h) Bit Reset CPU Access 7 0 R 6 0 R 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Note: R = Read Only; R/W = Read/Write.
Bit Position [7:6] 5 MDM
Value 00b 0 1 0 1
Description Reserved--must be 00b. MULTIDROP mode disabled. MULTIDROP mode enabled. See Table 64 for parity select definitions. LOOP BACK mode is not enabled. LOOP BACK mode is enabled. The UART operates in internal LOOP BACK mode. The transmit data output port is disconnected from the internal transmit data output and set to 1. The receive data input port is disconnected and internal receive data is connected to internal transmit data. The modem status input ports are disconnected and the four bits of the modem control register are connected as modem status inputs. The two modem control output ports (OUT1&2) are set to their inactive state No function in normal operation. In LOOP BACK mode, this bit is connected to the DCD bit in the UART Status Register. No function in normal operation. In LOOP BACK mode, this bit is connected to the RI bit in the UART Status Register. Request To Send In normal operation, the RTS output port is the inverse of this bit. In LOOP BACK mode, this bit is connected to the CTS bit in the UART Status Register. Data Terminal Ready In normal operation, the DTR output port is the inverse of this bit. In LOOP BACK mode, this bit is connected to the DSR bit in the UART Status Register.
4 LOOP
3 OUT2 2 OUT1 1 RTS
0-1
0-1
0-1
0 DTR
0-1
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UART Line Status Register This register is used to show the status of UART interrupts and registers. See Table 66.
Table 66. UART Line Status Registers (UART0_LSR = 00C5h, UART1_LSR = 00 D5h) Bit Reset CPU Access
Note: R = Read only.
7 0 R
6 1 R
5 1 R
4 0 R
3 0 R
2 0 R
1 0 R
0 0 R
Bit Position 7 ERR
Value 0
Description Always 0 when operating in with the FIFO disabled. With the FIFO enabled, this bit is reset when the UARTx_LSR register is read and there are no more bytes with error status in the FIFO. Error detected in the FIFO. There is at least 1 parity, framing or break indication error in the FIFO. Transmit holding register/FIFO is not empty or transmit shift register is not empty or transmitter is not idle. Transmit holding register/FIFO and transmit shift register are empty; and the transmitter is idle. This bit cannot be set to 1 during the BREAK condition. This bit only becomes 1 after the BREAK command is removed. Transmit holding register/FIFO is not empty. Transmit holding register/FIFO is empty. This bit cannot be set to 1 during the BREAK condition. This bit only becomes 1 after the BREAK command is removed. Receiver does not detect a BREAK condition. This bit is reset to 0 when the UARTx_LSR register is read. Receiver detects a BREAK condition on the receive input line. This bit is 1 if the duration of BREAK condition on the receive data is longer than one character transmission time, the time depends on the programming of the UARTx_LSR register. In case of FIFO only one null character is loaded into the receiver FIFO with the framing error. The framing error is revealed to the CPU whenever that particular data is read from the receiver FIFO.
1 6 TEMT 0 1
5 THRE
0 1
4 BI
0 1
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Bit Position 3 FE
Value 0 1
Description No framing error detected for character at the top of the FIFO. This bit is reset to 0 when the UARTx_LSR register is read. Framing error detected for the character at the top of the FIFO. This bit is set to 1 when the stop bit following the data/ parity bit is logic 0. The received character at the top of the FIFO does not contain a parity error. In multidrop mode, this indicates that the received character is a data byte. This bit is reset to 0 when the UARTx_LSR register is read. The received character at the top of the FIFO contains a parity error. In multidrop mode, this indicates that the received character is an address byte. The received character at the top of the FIFO does not contain an overrun error. This bit is reset to 0 when the UARTx_LSR register is read. Overrun error is detected. If the FIFO is not enabled, this indicates that the data in the receive buffer register was not read before the next character was transferred into the receiver buffer register. If the FIFO is enabled, this indicates the FIFO was already full when an additional character was received by the receiver shift register. The character in the receiver shift register is not put into the receiver FIFO. This bit is reset to 0 when the UARTx_RBR register is read or all bytes are read from the receiver FIFO. Data Ready If the FIFO is not enabled, this bit is set to 1 when a complete incoming character is transferred into the receiver buffer register from the receiver shift register. If the FIFO is enabled, this bit is set to 1 when a character is received and transferred to the receiver FIFO.
2 PE
0
1
1 OE
0
1
0 DR
0 1
UART Modem Status Register This register is used to show the status of the UART signals. See Table 67.
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Table 67. UART Modem Status Registers (UART0_MSR = 00C6h, UART1_MSR = 00 D6h) Bit Reset CPU Access
Note: R = Read only.
7 X R
6 X R
5 X R
4 X R
3 X R
2 X R
1 X R
0 X R
Bit Position 7 DCD
Value 0-1
Description Data Carrier Detect In NORMAL mode, this bit reflects the inverted state of the DCDx input pin. In LOOP BACK mode, this bit reflects the value of the UARTx_MCTL[3] = out2. Ring Indicator In NORMAL mode, this bit reflects the inverted state of the RIx input pin. In LOOP BACK mode, this bit reflects the value of the UARTx_MCTL[2] = out1. Data Set Ready In NORMAL mode, this bit reflects the inverted state of the DSRx input pin. In LOOP BACK mode, this bit reflects the value of the UARTx_MCTL[0] = DTR. Clear To Send In NORMAL mode, this bit reflects the inverted state of the CTSx input pin. In LOOP BACK mode, this bit reflects the value of the UARTx_MCTL[1] = RTS. Delta Status Change of DCD This bit is set to 1 whenever the DCDx pin changes state. This bit is reset to 0 when the UARTx_MSR register is read. Trailing Edge Change on RI This bit is set to 1 whenever a falling edge is detected on the RIx pin. This bit is reset to 0 when the UARTx_MSR register is read. Delta Status Change of DSR This bit is set to 1 whenever the DSRx pin changes state. This bit is reset to 0 when the UARTx_MSR register is read. Delta Status Change of CTS This bit is set to 1 whenever the CTSx pin changes state. This bit is reset to 0 when the UARTx_MSR register is read.
6 RI
0-1
5 DSR
0-1
4 CTS
0-1
3 DDCD 2 TERI
0-1
0-1
1 DDSR 0 DCTS
0-1
0-1
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UART Scratch Pad Register The UARTx_SPR register can be used by the system as a general-purpose Read/Write register. See Table 68.
Table 68. UART Scratch Pad Registers (UART0_SPR = 00C7h, UART1_SPR = 00D7h) Bit Reset CPU Access
Note: R/W = Read/Write.
7 0 R/W
6 0 R/W
5 0 R/W
4 0 R/W
3 0 R/W
2 0 R/W
1 0 R/W
0 0 R/W
Bit Position [7:0] SPR
Value 00h- FFh
Description The UART scratch pad register is available for use as a general-purpose Read/Write register.
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Infrared Encoder/Decoder
The EZ80F92 device contains a UART to infrared encoder/decoder (endec). The IrDA endec is integrated with the on-chip UART0 to allow easy communication between the CPU and IrDA Physical Layer Specification Version 1.4-compatible infrared transceivers, as illustrated in Figure 25. Infrared communication provides secure, reliable, high-speed, low-cost, point-to-point communication between PCs, PDAs, mobile telephones, printers, and other infrared-enabled devices.
EZ80F92
System Clock
Infrared Transceiver RxD TxD UART0 Baud Rate Clock Infrared Encoder/Decoder IR_RxD IR_TxD RxD TxD
Interrupt I/O Signal Address
Data
I/O Data Address
To eZ80 CPU
Figure 25.Infrared System Block Diagram
Functional Description
When the IrDA endec is enabled, the transmit data from the on-chip UART is encoded as digital signals in accordance with the IrDA standard and output to the infrared transceiver. Likewise, data received from the infrared transceiver is decoded by the endec and passed to the UART. Communication is half-duplex, meaning that simultaneous data transmission and reception is not allowed. The baud rate is set by the UART Baud Rate Generator, and supports IrDA standard baud rates from 9600 bps to 115.2 kbps. Higher baud rates than 115.2 kbps are possible, but do not meet IrDA specifications for these data rates. The UART must be enabled to use the
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endec. Refer to the Universal Asynchronous Receiver/Transmitter section on page 104 for more information about the UART and its Baud Rate Generator.
Transmit
The data to be transmitted via the IR transceiver is first sent to UART0. The UART transmit signal (TxD) and Baud Rate Clock are used by the IrDA endec to generate the modulation signal (IR_TxD) that drives the infrared transceiver. To enable transmit encoding, the IR_RxEN bit in the IR_CTL register must be set to 0. Each UART bit is 16-clocks wide. If the data to be transmitted is a logical 1 (High), the IR_TxD signal remains Low (0) for the full 16-clock period. If the data to be transmitted is a logical 0, a 3-clock High (1) pulse is output following a 7-clock Low (0) period. Following the 3-clock High pulse, a 6-clock Low pulse completes the full 16-clock data period. Data transmission is illustrated in Figure 26. During data transmission, the IR receive function should be disabled by clearing the IR_RxEN bit in the IR_CTL reg to 0. The SIR data format uses half-duplex communication; the UART does not transmit data while the receiver decoder is enabled.
16-clock period Baud Rate Clock
UART_TxD
Start Bit = 0 3-clock pulse
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_TxD 7-clock delay
Figure 26.Infrared Data Transmission
Receive
Data is received from the IR transceiver via the IR_RxD signal and decoded by the IrDA endec. This decoded data is passed from the endec to UART0. To enable receiver decode, the IR_RxEN bit in the IR_CTL register must be set to 1. The SIR data format uses halfduplex communication; therefore, the UART should not transmit data during normal operation while the receiver decoder is enabled.
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The UART baud rate clock is used by the IrDA endec to generate the demodulated signal (RxD) that drives the UART. Each UART bit period is sixteen baud-clocks wide. Each IR_RXD bit is encoded during a bit period such that a 0 is represented by a pulse and a 1 is represented by no pulse. The IrDA Physical Layer Specification describes a nominal pulse as being 3/16 of a bit period wide. In this case, if the data to be received is a logical 0 (Low), a 3-clock-wide Low (0) pulse is received following a 7-clock High (1) period. Following the 3-clock Low pulse is a 6-clock High pulse to complete the full 16-clock data period. If the data to be received is a logical 1 (High), the IR_RxD signal is held High (1) for the full 16-clock period. Data reception is illustrated in Figure 27.
16-clock period Baud Rate Clock Start Bit = 0 IR RxD 1.4 s min. pulse Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
UART RxD 16-clock period 16-clock period 16-clock period 16-clock period
8-clock delay
Figure 27.Infrared Data Reception
The IrDA Physical Layer Specification allows for a minimum signal width as well as the nominal signal width described above. By definition, the received pulse duration can be as small as 1.41 seconds for all baud rates up to 115.2 KBPS. Table 69 outlines the minimum and maximum pulse durations for all baud rates supported by the eZ80(R) CPU. A receiver frequency divider based upon the system clock frequency measures this time limit and allows legal signals to pass to UART0.
Table 69. IrDA Physical Layer 1.4 Pulse Durations Specifications Minimum Pulse Width 1.41 s 1.41 s 1.41 s Maximum Pulse Width 22.13 s 11.07 s 5.96 s
Baud Rate 9600 19200 38400
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Table 69. IrDA Physical Layer 1.4 Pulse Durations Specifications Minimum Pulse Width 1.41 s 1.41 s Maximum Pulse Width 4.34 s 2.23 s
Baud Rate 57600 115200
Receiver Frequency Divider
The IrDA receiver uses a 6-bit frequency divider. The value is derived from the system clock to measure IR_RxD pulses. The IrDA endec detects pulses that are within the IrDA Physical Layer specified minimum and maximum ranges, with system clock frequencies from 5 MHz up to 50 MHz. The upper four bits of the frequency divider factor are set via the FREQ_DIV bit in the IR_CTL register, based on the following equation:
Frequency Divider Factor = System Clock Frequency (MHz) Target Frequency of 3.33 MHz
The remaining lower two bits of the divider are set to 03h. The target frequency corresponds to a period of 1.2 seconds. The FREQ_DIV value must be rounded to the nearest integer and the resulting period of the 6-bit frequency divider must not be larger than 1.4 seconds, which is the IrDA defined minimum pulse width. If the period is greater than 1.4 seconds, FREQ_DIV should be rounded to the next lower integer. The receiver frequency divider value versus the system clock frequency is shown in Table 2, below.
Table 70. Frequency Divider Values System Clock < 5.0 MHz 5.0-7.8 MHz 7.8-10.8 MHz 10.8-13.6 MHz 13.6-25 MHz 25-50 MHz FREQ_DIV 00h* 01h 02h 03h FLOOR[4-bit Frequency Divider Factor] ROUND[4-bit Frequency Divider Factor]
Note: *The frequency divider is disabled when set to 00h.
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Setting the upper 4 bits of IR_CTL to 00h disables the frequency divider but not the IrDA receiver. In this mode, the IrDA receiver uses edge detection on the IR_RxD bit stream.
Jitter
Due to the inherent sampling of the received IR_RxD signal by the BIt Rate Clock, some jitter can be expected on the first bit in any sequence of data. However, all subsequent bits in the received data stream are a fixed 16 clock periods wide.
Infrared Encoder/Decoder Signal Pins
The IrDA endec signal pins (IR_TxD and IR_RxD) are multiplexed with General-Purpose I/O (GPIO) pins. These GPIO pins must be configured for alternate function operation for the endec to operate. The remaining six UART0 pins (CTS0, DCD0, DSR0, DTR0, RTS and RI0) are not required for use with the endec. The UART0 modem status interrupt should be disabled to prevent unwanted interrupts from these pins. The GPIO pins corresponding to these six unused UART0 pins can be used for inputs, outputs, or interrupt sources. Recommended GPIO Port D control register settings are provided in Table 71. Refer to the General-Purpose Input/Output section on page 40 for additional information about setting the GPIO Port modes.
Table 71. GPIO Mode Selection when using the IrDA Encoder/Decoder Allowable GPIO Port Mode 7 7 Any other than GPIO Mode 7 (1, 2, 3, 4, 5, 6, 8, or 9)
GPIO Port D Bits PD0 PD1 PD2-PD7
Allowable Port Mode Functions Alternate function. Alternate function. Output, input, open-drain, open-source, levelsensitive interrupt input, or edge-triggered interrupt input.
Loopback Testing
Both internal and external loopback testing can be accomplished with the IrDA endec on the EZ80F92 device. Setting the LOOP_BACK bit to 1 enables internal loopback testing. During internal loopback, the IR_TxD output signal is inverted and connected on-chip to the IR_RxD input. External loopback testing of the off-chip IrDA transceiver can be accomplished by transmitting data from the UART while the receiver is enabled (IR_RxEN set to 1).
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Infrared Encoder/Decoder Register After a RESET, the Infrared Encoder/Decoder register is set to its default value. Any writes to unused register bits are ignored and reads return a value of 0. The IR_CTL register is described in Table 72.
Table 72. Infrared Encoder/Decoder Control Registers (IR_CTL = 00BFh) Bit Reset CPU Access 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Note: R = Read only; R/W = Read/Write.
Bit Position [7:3] 2 LOOP_BACK
Value
Description
000000 Reserved. 0 1 Internal LOOP BACK mode is disabled. Internal LOOP BACK mode is enabled. IR_TxD output is inverted and connected to IR_RxD input for internal loop back testing. IR_RxD data is ignored. IR_RxD data is passed to UART0 RxD. IrDA endec is disabled. IrDA endec is enabled.
1 IR_RxEN 0 IR_EN
0 1 0 1
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Serial Peripheral Interface
The Serial Peripheral Interface (SPI) is a synchronous interface allowing several SPI-type devices to be interconnected. The SPI is a full-duplex, synchronous, character-oriented communication channel that employs a four-wire interface. The SPI block consists of a transmitter, receiver, baud rate generator, and control unit. During an SPI transfer, data is sent and received simultaneously by both the master and the slave SPI devices. In a serial peripheral interface, separate signals are required for data and clock. The SPI may be configured as either a master or a slave. The connection of two SPI devices (one master and one slave) and the direction of data transfer is demonstrated in Figures 28 and 29 .
MASTER
SS
DATAIN
MISO
Bit 0
Bit 7 SCK
DATAOUT CLKOUT
8-Bit Shift Register
Baud Rate Generator
Figure 28.SPI Master Device
SLAVE
ENABLE SS
DATAIN CLKIN
MOSI SCK
Bit 0
Bit 7
MISO
DATAOUT
8-Bit Shift Register
Figure 29.SPI Slave Device
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SPI Signals
The four basic SPI signals are:
* * * *
MISO (Master In, Slave Out) MOSI (Master Out, Slave In) SCK (SPI Serial Clock) SS (Slave Select)
These SPI signals are discussed in the following paragraphs. Each signal is described in both MASTER and SLAVE modes. Master In, Slave Out The Master In, Slave Out (MISO) pin is configured as an input in a master device and as an output in a slave device. It is one of the two lines that transfer serial data, with the mostsignificant bit sent first. The MISO pin of a slave device is placed in a high-impedance state if the slave is not selected. When the SPI is not enabled, this signal is in a highimpedance state. Master Out, Slave In The Master Out, Slave In (MOSI) pin is configured as an output in a master device and as an input in a slave device. It is one of the two lines that transfer serial data, with the mostsignificant bit sent first. When the SPI is not enabled, this signal is in a high-impedance state. Slave Select The active Low Slave Select (SS) input signal is used to select the SPI as a slave device. It must be Low prior to all data communication and must stay Low for the duration of the data transfer. The SS input signal must be High for the SPI to operate as a master device. If the SS signal goes Low, a Mode Fault error flag (MODF) is set in the SPI_SR register. See the SPI Status Register (SPI_SR) on page 138 for more information. When the Clock Phase bit (CPHA) is set to 0, the shift clock is the logical OR of SS with SCK. In this clock phase mode, SS must go High between successive characters in an SPI message. When CPHA is set to 1, SS can remain Low for several SPI characters. In cases where there is only one SPI slave, its SS line could be tied Low as long as CPHA is set to 1. See the SPI Control Register (SPI_CTL) on page 137 for more information about CPHA. Serial Clock The Serial Clock (SCK) is used to synchronize data movement both in and out of the device through its MOSI and MISO pins. The master and slave are each capable of
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exchanging a byte of data during a sequence of eight clock cycles. Because SCK is generated by the master, the SCK pin becomes an input on a slave device. The SPI contains an internal divide-by-two clock divider. In MASTER mode, the SPI serial clock is one-half the frequency of the clock signal created by the SPI's Baud Rate Generator. As demonstrated in Figure 30 and Table 73, four possible timing relations may be chosen by using control bits CPOL and CPHA in the SPI Control register. See the SPI Control Register (SPI_CTL) on page 137. Both the master and slave must operate with the identical timing, clock polarity (CPOL), and clock phase (CPHA). The master device always places data on the MOSI line a half-cycle before the clock edge (SCK signal) so that the slave device latches the data.
Number of Cycles on the SCK Signal 1 2 3 4 5 6 7 8
SCK (CPOL bit = 0) SCK (CPOL bit = 1)
Sample Input (CPHA bit = 0) Data Out
MSB
6
5
4
3
2
1
LSB
Sample Input (CPHA bit = 1) Data Out ENABLE (To Slave)
MSB
6
5
4
3
2
1
LSB
Figure 30.SPI Timing
Table 73. SPI Clock Phase and Clock Polarity Operation SS High SCK Transmit Edge Falling Rising Rising Falling SCK Receive Edge Rising Falling Falling Rising SCK Idle State Low High Low High Between Characters? Yes Yes No No
CPHA 0 0 1 1
CPOL 0 1 0 1
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SPI Functional Description
When a master transmits to a slave device via the MOSI signal, the slave device responds by sending data to the master via the master's MISO signal. The resulting implication is a full-duplex transmission, with both data out and data in synchronized with the same clock signal. Thus the byte transmitted is replaced by the byte received and eliminates the requirement for separate transmit-empty and receive-full status bits. A single status bit, SPIF, is used to signify that the I/O operation is completed, see the SPI Status Register (SPI_SR) on page 138. The SPI is double-buffered on Read, but not on Write. If a Write is performed during data transfer, the transfer occurs uninterrupted, and the Write is unsuccessful. This condition causes the WRITE COLLISION (WCOL) status bit in the SPI_SR register to be set. After a data byte is shifted, the SPIF flag of the SPI_SR register is set. In SPI MASTER mode, the SCK pin functions as an output. It idles High or Low, depending on the CPOL bit in the SPI_CTL register, until data is written to the shift register. Data transfer is initiated by writing to the transmit shift register, SPI_TSR. Eight clocks are then generated to shift the eight bits of transmit data out the MOSI pin while shifting in eight bits of data on the MISO pin. After transfer, the SCK signal idles. In SPI SLAVE mode, the start logic receives a logic Low from the SS pin and a clock input at the SCK pin, and the slave is synchronized to the master. Data from the master is received serially from the slave MOSI signal and loads the 8-bit shift register. After the 8bit shift register is loaded, its data is parallel transferred to the Read buffer. During a Write cycle data is written into the shift register, then the slave waits for the SPI master to initiate a data transfer, supply a clock signal, and shift the data out on the slave's MISO signal. If the CPHA bit in the SPI_CTL register is 0, a transfer begins when SS pin signal goes Low and the transfer ends when SS goes High after eight clock cycles on SCK. When the CPHA bit is set to 1, a transfer begins the first time SCK becomes active while SS is Low and the transfer ends when the SPIF flag gets set.
SPI Flags
Mode Fault The Mode Fault flag (MODF) indicates that there may be a multimaster conflict for system control. The MODF bit is normally cleared to 0 and is only set to 1 when the master device's SS pin is pulled Low. When a mode fault is detected, the following occurs: 1. The MODF flag (SPI_SR[4]) is set to 1. 2. The SPI device is disabled by clearing the SPI_EN bit (SPI_CTL[5]) to 0. 3. The MASTER_EN bit (SPI_CTL[4]) is cleared to 0, forcing the device into SLAVE mode.
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4. If the SPI interrupt is enabled by setting IRQ_EN (SPI_CTL[7]) High, an SPI interrupt is generated. Clearing the Mode Fault flag is performed by reading the SPI Status register. The other SPI control bits (SPI_EN and MASTER_EN) must be restored to their original states by user software after the Mode Fault flag is cleared. Write Collision The WRITE COLLISION flag, WCOL (SPI_SR[5]), is set to 1 when an attempt is made to write to the SPI Transmit Shift register (SPI_TSR) while data transfer occurs. Clearing the WCOL bit is performed by reading SPI_SR with the WCOL bit set.
SPI Baud Rate Generator
The SPI's Baud Rate Generator creates a lower frequency clock from the high-frequency system clock. The Baud Rate Generator output is used as the clock source by the SPI. Baud Rate Generator Functional Description The SPI's Baud Rate Generator consists of a 16-bit downcounter, two 8-bit registers, and associated decoding logic. The Baud Rate Generator's initial value is defined by the two BRG Divisor Latch registers, {SPI_BRG_H, SPI_BRG_L}. At the rising edge of each system clock, the BRG decrements until it reaches the value 0001h. On the next system clock rising edge, the BRG reloads the initial value from {SPI_BRG_H, SPI_BRG_L) and outputs a pulse to indicate the end-of-count. Calculate the SPI Data Rate with the following equation:
SPI Data Rate (bits/s) = System Clock Frequency 2 X SPI Baud Rate Generator Divisor
Upon RESET, the 16-bit BRG divisor value resets to 0002h. When the SPI is operating as a Master, the BRG divisor value must be set to a value of 0003h or greater. When the SPI is operating as a Slave, the BRG divisor value must be set to a value of 0004h or greater. A software Write to either the Low- or High-byte registers for the BRG Divisor Latch causes both the Low and High bytes to load into the BRG counter, and causes the count to restart.
Data Transfer Procedure with SPI Configured as the Master
1. Load the SPI Baud Rate Generator Registers, SPI_BRG_H and SPI_BRG_L. 2. External device must deassert the SS pin if currently asserted. 3. Load the SPI Control Register, SPI_CTL.
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4. Assert the ENABLE pin of the slave device using a GPIO pin. 5. Load the SPI Transmit Shift Register, SPI_TSR. 6. When the SPI data transfer is complete, deassert the ENABLE pin of the slave device.
Data Transfer Procedure with SPI Configured as a Slave
1. Load the SPI Baud Rate Generator Registers, SPI_BRG_H and SPI_BRG_L. 2. Load the SPI Transmit Shift Register, SPI_TSR. This load cannot occur while the SPI slave is currently receiving data. 3. Wait for the external SPI Master device to initiate the data transfer by asserting SS.
SPI Registers
There are six registers in the Serial Peripheral Interface which provide control, status, and data storage functions. The SPI registers are described in the following paragraphs. SPI Baud Rate Generator Registers--Low Byte and High Byte These registers hold the Low and High bytes of the 16-bit divisor count loaded by the processor for baud rate generation. The 16-bit clock divisor value is returned by {SPI_BRG_H, SPI_BRG_L}. Upon RESET, the 16-bit BRG divisor value resets to 0002h. When configured as a Master, the 16-bit divisor value must be between 0003h and FFFFh, inclusive. When configured as a Slave, the 16-bit divisor value must be between 0004h and FFFFh, inclusive. A Write to either the Low or High byte registers for the BRG Divisor Latch causes both bytes to be loaded into the BRG counter and the count restarted. See Tables 74 and 75.
Table 74. SPI Baud Rate Generator Register--Low Byte (SPI_BRG_L = 00B8h) Bit Reset CPU Access
Note: R/W = Read/Write.
7 0 R/W
6 0 R/W
5 0 R/W
4 0 R/W
3 0 R/W
2 0 R/W
1 1 R/W
0 0 R/W
Bit Position [7:0] SPI_BRG_L
Value 00h- FFh
Description These bits represent the Low byte of the 16-bit Baud Rate Generator divider value. The complete BRG divisor value is returned by {SPI_BRG_H, SPI_BRG_L}.
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Table 75. SPI Baud Rate Generator Register--High Byte (SPI_BRG_H = 00B9h) Bit Reset CPU Access
Note: R/W = Read/Write.
7 0 R/W
6 0 R/W
5 0 R/W
4 0 R/W
3 0 R/W
2 0 R/W
1 0 R/W
0 0 R/W
Bit Position [7:0] SPI_BRG_H
Value 00h- FFh
Description These bits represent the High byte of the 16-bit Baud Rate Generator divider value. The complete BRG divisor value is returned by {SPI_BRG_H, SPI_BRG_L}.
SPI Control Register This register is used to control and setup the serial peripheral interface. The SPI should be disabled prior to making any changes to CPHA or CPOL. See Table 76.
Table 76. SPI Control Register (SPI_CTL = 00BAh) Bit Reset CPU Access 7 0 R/W 6 0 R 5 0 R/W 4 0 R/W 3 0 R/W 2 1 R/W 1 0 R 0 0 R
Note: R = Read Only; R/W = Read/Write.
Bit Position 7 IRQ_EN 6 5 SPI_EN 4 MASTER_EN 3 CPOL
Value Description 0 1 0 0 1 0 1 0 1 SPI system interrupt is disabled. SPI system interrupt is enabled. Reserved. SPI is disabled. SPI is enabled. When enabled, the SPI operates as a slave. When enabled, the SPI operates as a master. Master SCK pin idles in a Low (0) state. Master SCK pin idles in a High (1) state.
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Bit Position 2 CPHA [1:0]
Value Description 0 1 00 SS must go High after transfer of every byte of data. SS can remain Low to transfer any number of data bytes. Reserved.
SPI Status Register The SPI Status Read Only register returns the status of data transmitted using the serial peripheral interface. Reading the SPI_SR register clears Bits 7, 6, and 4 to a logical 0. See Table 77.
Table 77. SPI Status Register (SPI_SR = 00BBh) Bit Reset CPU Access
Note: R = Read Only.
7 0 R
6 0 R
5 0 R
4 0 R
3 0 R
2 0 R
1 0 R
0 0 R
Bit Position 7 SPIF
Value Description 0 1 SPI data transfer is not finished. SPI data transfer is finished. If enabled, an interrupt is generated. This bit flag is cleared to 0 by a Read of the SPI_SR register. An SPI write collision is not detected. An SPI write collision is detected. This bit flag is cleared to 0 by a Read of the SPI_SR registers. Reserved. A mode fault (multimaster conflict) is not detected. A mode fault (multimaster conflict) is detected. This bit flag is cleared to 0 by a Read of the SPI_SR register. Reserved.
6 WCOL
0 1 0 0 1 0000
5 4 MODF
[3:0]
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SPI Transmit Shift Register The SPI Transmit Shift register (SPI_TSR) is used by the SPI master to transmit data onto the SPI serial bus to the slave device. A Write to the SPI_TSR register places data directly into the shift register for transmission. A Write to this register within an SPI device configured as a master initiates transmission of the byte of the data loaded into the register. At the completion of transmitting a byte of data, the SPIF status bit (SPI_SR[7]) is set to 1 in both the master and slave devices. The SPI Transmit Shift Write Only register shares the same address space as the SPI Receive Buffer Read Only register. See Table 78.
Table 78. SPI Transmit Shift Register (SPI_TSR = 00BCh) Bit Reset CPU Access
Note: W = Write only.
7 X W
6 X W
5 X W
4 X W
3 X W
2 X W
1 X W
0 X W
Bit Position [7:0] TX_DATA
Value Description 00h- FFh SPI transmit data.
SPI Receive Buffer Register The SPI Receive Buffer register (SPI_RBR) is used by the SPI slave to receive data from the serial bus. The SPIF bit must be cleared prior to a second transfer of data from the shift register or an overrun condition exists. In cases of overrun the byte that caused the overrun is lost. The SPI Receive Buffer Read Only register shares the same address space as the SPI Transmit Shift Write Only register. See Table 79.
Table 79. SPI Receive Buffer Register (SPI_RBR = 00BCh) Bit Reset CPU Access
Note: R = Read Only.
7 X R
6 X R
5 X R
4 X R
3 X R
2 X R
1 X R
0 X R
Bit Position [7:0] RX_DATA
Value Description 00h- FFh SPI received data.
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I2C Serial I/O Interface
I2C General Characteristics
The I2C serial I/O bus is a two-wire communication interface that can operate in four modes:
* * * *
MASTER TRANSMIT MASTER RECEIVE SLAVE TRANSMIT SLAVE RECEIVE
The I2C interface consists of the Serial Clock (SCL) and the Serial Data (SDA). Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via an external pull-up resistor. When the bus is free, both lines are High. The output stages of devices connected to the bus must be configured as open-drain outputs. Data on the I2C bus can be transferred at a rate of up to 100 KBPS in STANDARD mode, or up to 400 KBPS in FAST mode. One clock pulse is generated for each data bit transferred. Clocking Overview If another device on the I2C bus drives the clock line when the I2C is in MASTER mode, the I2C synchronizes its clock to the I2C bus clock. The High period of the clock is determined by the device that generates the shortest High clock period. The Low period of the clock is determined by the device that generates the longest Low clock period. A slave may stretch the Low period of the clock to slow down the bus master. The Low period may also be stretched for handshaking purposes. This can be done after each bit transfer or each byte transfer. The I2C stretches the clock after each byte transfer until the IFLG bit in the I2C_CTL register is cleared. Bus Arbitration Overview In MASTER mode, the I2C checks that each transmitted logic 1 appears on the I2C bus as a logic 1. If another device on the bus overrules and pulls the SDA signal Low, arbitration is lost. If arbitration is lost during the transmission of a data byte or a Not-Acknowledge bit, the I2C returns to the idle state. If arbitration is lost during the transmission of an address, the I2C switches to SLAVE mode so that it can recognize its own slave address or the general call address.
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Data Validity The data on the SDA line must be stable during the High period of the clock. The High or Low state of the data line can only change when the clock signal on the SCL line is Low as illustrated in Figure 31.
SDA Signal SCL Signal Data Line Stable Data Valid Change of Data Allowed
Figure 31.I2C Clock and Data Relationship
START and STOP Conditions Within the I2C bus protocol, unique situations arise which are defined as START and STOP conditions. See Figure 32. A High-to-Low transition on the SDA line while SCL is High indicates a START condition. A Low-to-High transition on the SDA line while SCL is High defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free a defined time after the STOP condition.
SDA Signal
SCL Signal S START Condition P STOP Condition
Figure 32.START and STOP Conditions In I2C Protocol
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Transferring Data
Byte Format Every character transferred on the SDA line must be a single 8-bit byte. The number of bytes that can be transmitted per transfer is unrestricted. Each byte must be followed by an Acknowledge (ACK)1. Data is transferred with the most-significant bit (msb) first. See Figure 33. A receiver can hold the SCL line Low to force the transmitter into a wait state. Data transfer then continues when the receiver is ready for another byte of data and releases SCL.
SDA Signal
MSB Acknowledge from Receiver 2 8 9 1 Acknowledge from Receiver 9 ACK
SCL Signal S START Condition
1
P STOP Condition
Clock Line Held Low By Receiver
Figure 33.I2C Frame Structure
Acknowledge Data transfer with an ACK function is obligatory. The ACK-related clock pulse is generated by the master. The transmitter releases the SDA line (High) during the ACK clock pulse. The receiver must pull down the SDA line during the ACK clock pulse so that it remains stable Low during the High period of this clock pulse. See Figure 34. A receiver that is addressed is obliged to generate an ACK after each byte is received. When a slave-receiver doesn't acknowledge the slave address (for example, unable to receive because it's performing some real-time function), the data line must be left High by the slave. The master then generates a STOP condition to abort the transfer. If a slave-receiver acknowledges the slave address, but cannot receive any more data bytes, the master must abort the transfer. The abort is indicated by the slave generating the Not Acknowledge (NACK) on the first byte to follow. The slave leaves the data line High and the master generates the STOP condition. If a master-receiver is involved in a transfer, it must signal the end of data to the slavetransmitter by not generating an ACK on the final byte that is clocked out of the slave. The
1. ACK is defined as a general Acknowledge bit. By contrast, the I2C Acknowledge bit is represented as AAK, bit 2 of the I2C Control Register, which identifies which ACK signal to transmit. See Table 89 on page 156.
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slave-transmitter must release the data line to allow the master to generate a STOP or a repeated START condition.
Data Output by Transmitter MSB Data Output by Receiver SCL Signal from Master
1
S
1 2 8 9
START Condition Clock Pulse for Acknowledge
Figure 34.I2C Acknowledge
Clock Synchronization
All masters generate their own clocks on the SCL line to transfer messages on the I2C bus. Data is only valid during the High period of each clock. Clock synchronization is performed using the wired AND connection of the I2C interfaces to the SCL line, meaning that a High-to-Low transition on the SCL line causes the relevant devices to start counting from their Low period. When a device clock goes Low, it holds the SCL line in that state until the clock High state is reached. See Figure 35. The Low-toHigh transition of this clock, however, may not change the state of the SCL line if another clock is still within its Low period. The SCL line is held Low by the device with the longest Low period. Devices with shorter Low periods enter a High wait-state during this time. When all devices concerned count off their Low period, the clock line is released and goes High. There is no difference between the device clocks and the state of the SCL line, and all of the devices start counting their High periods. The first device to complete its High period again pulls the SCL line Low. In this way, a synchronized SCL clock is generated with its Low period determined by the device with the longest clock Low period, and its High period determined by the one with the shortest clock High period.
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Wait State CLK1 Signal Counter Reset CLK2 Signal
Start Counting High Period
SCL Signal
Figure 35.Clock Synchronization In I2C Protocol
Arbitration A master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold time of the START condition which results in a defined START condition to the bus. Arbitration takes place on the SDA line, while the SCL line is at the High level, in such a way that the master which transmits a High level, while another master is transmitting a Low level switches off its data output stage because the level on the bus doesn't correspond to its own level. Arbitration can continue for many bits. Its first stage is comparison of the address bits. If the masters are each trying to address the same device, arbitration continues with comparison of the data. Because address and data information about the I2C bus is used for arbitration, no information is lost during this process. A master which loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration. If a master also incorporates a slave function and it loses arbitration during the addressing stage, it's possible that the winning master is trying to address it. The losing master must switch over immediately to its slave-receiver mode. Figure 35 illustrates the arbitration procedure for two masters. Of course, more may be involved (depending on how many masters are connected to the bus). The moment there is a difference between the internal data level of the master generating DATA 1 and the actual level on the SDA line, its data output is switched off, which means that a High output level is then connected to the bus. As a result, the data transfer initiated by the winning master is not affected. Because control of the I2C bus is decided solely on the address and data sent by competing masters, there is no central master, nor any order of priority on the bus. Special attention must be paid if, during a serial transfer, the arbitration procedure is still in progress at the moment when a repeated START condition or a STOP condition is transmitted to the I2C bus. If it is possible for such a situation to occur, the masters involved must send this repeated START condition or STOP condition at the same position in the format frame. In other words, arbitration is not allowed between:
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* *
A STOP condition and a data bit A repeated START condition and a STOP condition
Clock Synchronization for Handshake The Clock synchronizing mechanism can function as a handshake, enabling receivers to cope with fast data transfers, on either a byte or bit level. The byte level allows a device to receive a byte of data at a fast rate, but allows the device more time to store the received byte or to prepare another byte for transmission. Slaves hold the SCL line Low after reception and acknowledge the byte, forcing the master into a wait state until the slave is ready for the next byte transfer in a handshake procedure.
Operating Modes
Master Transmit In MASTER TRANSMIT mode, the I2C transmits a number of bytes to a slave receiver. Enter MASTER TRANSMIT mode by setting the STA bit in the I2C_CTL register to 1. The I2C then tests the I2C bus and transmits a START condition when the bus is free. When a START condition is transmitted, the IFLG bit is 1 and the status code in the I2C_SR register is 08h. Before this interrupt is serviced, the I2C_DR register must be loaded with either a 7-bit slave address or the first part of a 10-bit slave address, with the lsb cleared to 0 to specify TRANSMIT mode. The IFLG bit should now be cleared to 0 to prompt the transfer to continue. After the 7-bit slave address (or the first part of a 10-bit address) plus the Write bit are transmitted, the IFLG is set again. A number of status codes are possible in the I2C_SR register. See Table 80.
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Table 80. I2C Master Transmit Status Codes Code 18h I2C State Addr+W transmitted, ACK received Microcontroller Response Next I2C Action For a 7-bit address: write byte to DATA, clear IFLG Or set STA, clear IFLG Or set STP, clear IFLG Or set STA & STP, clear IFLG For a 10-bit address: write extended address byte to DATA, clear IFLG 20h 38h Addr+W transmitted, ACK not received Arbitration lost Same as code 18h Clear IFLG Or set STA, clear IFLG 68h Arbitration lost, +W received, ACK transmitted Clear IFLG, AAK = 0 Or clear IFLG, AAK = 1 Same as code 68h Transmit data byte, receive ACK Transmit repeated START Transmit STOP Transmit STOP then START Transmit extended address byte Same as code 18h Return to idle Transmit START when bus is free Receive data byte, transmit NACK Receive data byte, transmit ACK Same as code 68h
78h
Arbitration lost, General call addr received, ACK transmitted Arbitration lost, SLA+R received, ACK transmitted
B0h
Write byte to DATA, clear IFLG, clear AAK = 0
Transmit last byte, receive ACK
Or write byte to DATA, clear Transmit data byte, IFLG, set AAK = 1 receive ACK
W = Write bit; that is, the lsb is cleared to 0.
If 10-bit addressing is being used, then the status code is 18h or 20h after the first part of a 10-bit address plus the Write bit are successfully transmitted. After this interrupt is serviced and the second part of the 10-bit address is transmitted, the I2C_SR register contains one of the codes in Table 81.
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Table 81. I2C 10-Bit Master Transmit Status Codes Code 38h I2C State Arbitration lost Microcontroller Response Clear IFLG Or set STA, clear IFLG 68h Arbitration lost, SLA+W received, ACK transmitted Clear IFLG, clear AAK = 0 Or clear IFLG, set AAK = 1 Write byte to DATA, clear IFLG, clear AAK = 0 Or write byte to DATA, clear IFLG, set AAK = 1 Next I2C Action Return to idle Transmit START when bus free Receive data byte, transmit NACK Receive data byte, transmit ACK Transmit last byte, receive ACK Transmit data byte, receive ACK Transmit data byte, receive ACK Transmit repeated START Transmit STOP Transmit STOP then START Same as code D0h
B0h
Arbitration lost, SLA+R received, ACK transmitted
D0h
Second Address byte Write byte to DATA, + W transmitted, clear IFLG ACK received Or set STA, clear IFLG Or set STP, clear IFLG Or set STA & STP, clear IFLG
D8h
Second Address byte Same as code D0h + W transmitted, ACK not received
If a repeated START condition is transmitted, the status code is 10h instead of 08h. After each data byte is transmitted, the IFLG is 1 and one of the status codes listed in Table 82 is in the I2C_SR register.
Table 82. I2C Master Transmit Status Codes For Data Bytes Code I2C State 28h Data byte transmitted, ACK received Microcontroller Response Next I2C Action Write byte to DATA, clear IFLG Or set STA, clear IFLG Or set STP, clear IFLG Or set STA & STP, clear IFLG Transmit data byte, receive ACK Transmit repeated START Transmit STOP Transmit START then STOP
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Table 82. I2C Master Transmit Status Codes For Data Bytes (Continued) Code I2C State 30h Data byte transmitted, ACK not received Arbitration lost Microcontroller Response Next I2C Action Same as code 28h Same as code 28h
38h
Clear IFLG Or set STA, clear IFLG
Return to idle Transmit START when bus free
When all bytes are transmitted, the microcontroller should write a 1 to the STP bit in the I2C_CTL register. The I2C then transmits a STOP condition, clears the STP bit and returns to the idle state. Master Receive In MASTER RECEIVE mode, the I2C receives a number of bytes from a slave transmitter. After the START condition is transmitted, the IFLG bit is 1 and the status code 08h is loaded in the I2C_SR register. The I2C_DR register should be loaded with the slave address (or the first part of a 10-bit slave address), with the lsb set to 1 to signify a Read. The IFLG bit should be cleared to 0 as a prompt for the transfer to continue. When the 7-bit slave address (or the first part of a 10-bit address) and the Read bit are transmitted, the IFLG bit is set and one of the status codes listed in Table 83 is in the I2C_SR register.
Table 83. I2C Master Receive Status Codes Code 40h I2C State Addr + R transmitted, ACK received Microcontroller Response Next I2C Action For a 7-bit address, clear IFLG, AAK = 0 Or clear IFLG, AAK = 1 For a 10-bit address Write extended address byte to DATA, clear IFLG R = Read bit; that is, the lsb is set to 1. Receive data byte, transmit NACK Receive data byte, transmit ACK Transmit extended address byte
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Table 83. I2C Master Receive Status Codes Code 48h I2C State Addr + R transmitted, ACK not received Microcontroller Response Next I2C Action For a 7-bit address: Set STA, clear IFLG Or set STP, clear IFLG Or set STA & STP, clear IFLG For a 10-bit address: Write extended address byte to DATA, clear IFLG 38h Arbitration lost Clear IFLG Or set STA, clear IFLG 68h Arbitration lost, SLA+W received, ACK transmitted Clear IFLG, clear AAK = 0 Or clear IFLG, set AAK = 1 Same as code 68h Transmit repeated START Transmit STOP Transmit STOP then START Transmit extended address byte Return to idle Transmit START when bus is free Receive data byte, transmit NACK Receive data byte, transmit ACK Same as code 68h
78h
Arbitration lost, General call addr received, ACK transmitted Arbitration lost, SLA+R received, ACK transmitted
B0h
Write byte to DATA, clear IFLG, clear AAK = 0 Or write byte to DATA, clear IFLG, set AAK = 1
Transmit last byte, receive ACK Transmit data byte, receive ACK
R = Read bit; that is, the lsb is set to 1.
If 10-bit addressing is being used, the slave is first addressed using the full 10-bit address plus the Write bit. The master then issues a restart followed by the first part of the 10-bit address again, but with the Read bit. The status code then becomes 40h or 48h. It is the responsibility of the slave to remember that it had been selected prior to the restart. If a repeated START condition is received, the status code is 10h instead of 08h. After each data byte is received, the IFLG is set and one of the status codes listed in Table 84 is in the I2C_SR register.
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Table 84. I2C Master Receive Status Codes For Data Bytes Code 50h I2C State Microcontroller Response Next I2C Action Receive data byte, transmit NACK Receive data byte, transmit ACK Transmit repeated START Transmit STOP Transmit STOP then START Same as master transmit
Data byte received, Read DATA, clear IFLG, ACK transmitted clear AAK = 0 Or read DATA, clear IFLG, set AAK = 1
58h
Data byte received, Read DATA, set STA, NACK transmitted clear IFLG Or read DATA, set STP, clear IFLG Or read DATA, set STA & STP, clear IFLG
38h
Arbitration lost in NACK bit
Same as master transmit
When all bytes are received, a NACK should be sent, then the microcontroller should write a 1 to the STP bit in the I2C_CTL register. The I2C then transmits a STOP condition, clears the STP bit and returns to the idle state. Slave Transmit In SLAVE TRANSMIT mode, a number of bytes are transmitted to a master receiver. The I2C enters SLAVE TRANSMIT mode when it receives its own slave address and a Read bit after a START condition. The I2C then transmits an acknowledge bit (if the AAK bit is set to 1) and sets the IFLG bit in the I2C_CTL register and the I2C_SR register contains the status code A8h. Note: When I2C contains a 10-bit slave address (signified by F0h-F7h in the I2C_SAR register), it transmits an acknowledge after the first address byte is received after a restart. An interrupt is generated, IFLG is set but the status does not change. No second address byte is sent by the master. It is up to the slave to remember it had been selected prior to the restart. I2C goes from MASTER mode to SLAVE TRANSMIT mode when arbitration is lost during the transmission of an address, and the slave address and Read bit are received. This action is represented by the status code B0h in the I2C_SR register. The data byte to be transmitted is loaded into the I2C_DR register and the IFLG bit cleared. After the I2C transmits the byte and receives an acknowledge, the IFLG bit is set and the I2C_SR register contains B8h. When the final byte to be transmitted is loaded into the I2C_DR register, the AAK bit is cleared when the IFLG is cleared. After the final byte
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is transmitted, the IFLG is set and the I2C_SR register contains C8h and the I2C returns to the idle state. The AAK bit must be set to 1 before reentering SLAVE mode. If no acknowledge is received after transmitting a byte, the IFLG is set and the I2C_SR register contains C0h. The I2C then returns to the idle state. If a STOP condition is detected after an acknowledge bit, the I2C returns to the idle state. Slave Receive In SLAVE RECEIVE mode, a number of data bytes are received from a master transmitter. The I2C enters SLAVE RECEIVE mode when it receives its own slave address and a Write bit (lsb = 0) after a START condition. The I2C transmits an acknowledge bit and sets the IFLG bit in the I2C_CTL register and the I2C_SR register contains the status code 60h. The I2C also enters SLAVE RECEIVE mode when it receives the general call address 00h (if the GCE bit in the I2C_SAR register is set). The status code is then 70h. Note: When the I2C contains a 10-bit slave address (signified by F0h-F7h in the I2C_SAR register), it transmits an acknowledge after the first address byte is received but no interrupt is generated. IFLG is not set and the status does not change. The I2C generates an interrupt only after the second address byte is received. The I2C sets the IFLG bit and loads the status code as described above. I2C goes from MASTER mode to SLAVE RECEIVE mode when arbitration is lost during the transmission of an address, and the slave address and Write bit (or the general call address if the CGE bit in the I2C_SAR register is set to 1) are received. The status code in the I2C_SR register is 68h if the slave address is received or 78h if the general call address is received. The IFLG bit must be cleared to 0 to allow data transfer to continue. If the AAK bit in the I2C_CTL register is set to 1 then an acknowledge bit (Low level on SDA) is transmitted and the IFLG bit is set after each byte is received. The I2C_SR register contains the status code 80h or 90h if SLAVE RECEIVE mode is entered with the general call address. The received data byte can be read from the I2C_DR register and the IFLG bit must be cleared to allow the transfer to continue. If a STOP condition or a repeated START condition is detected after the acknowledge bit, the IFLG bit is set and the I2C_SR register contains status code A0h. If the AAK bit is cleared to 0 during a transfer, the I2C transmits a not-acknowledge bit (High level on SDA) after the next byte is received, and set the IFLG bit. The I2C_SR register contains the status code 88h or 98h if SLAVE RECEIVE mode is entered with the general call address. The I2C returns to the idle state when the IFLG bit is cleared to 0.
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I2C Registers
Addressing The processor interface provides access to six 8-bit registers: four Read/Write registers, one Read Only register and two Write Only registers, as indicated in Table 85.
Table 85. I2C Register Descriptions Register I2C_SAR I2C_XSAR I2C_DR I2C_CTL I2C_SR I2C_CCR I2C_SRR Description Slave address register Extended slave address register Data byte register Control register Status register (Read Only) Clock Control register (Write Only) Software reset register (Write Only)
Resetting the I2C Registers Hardware reset. When the I2C is reset by a hardware reset of the EZ80F92 device, the I2C_SAR, I2C_XSAR, I2C_DR and I2C_CTL registers are cleared to 00h; while the I2C_SR register is set to F8h. Software Reset. Perform a software reset by writing any value to the I2C Software Reset
Register (I2C_SRR). A software reset sets the I2C back to idle and the STP, STA, and IFLG bits of the I2C_CTL register to 0. I2C Slave Address Register The I2C_SAR register provides the 7-bit address of the I2C when in SLAVE mode and allows 10-bit addressing in conjunction with the I2C_XSAR register. I2C_SAR[7:1] = sla[6:0] is the 7-bit address of the I2C when in 7-bit SLAVE mode. When the I2C receives this address after a START condition, it enters SLAVE mode. I2C_SAR[7] corresponds to the first bit received from the I2C bus. When the register receives an address starting with F7h to F0h (I2C_SAR[7:3] = 11110b), the I2C recognizes that a 10-bit slave addressing mode is being selected. The I2C sends an ACK after receiving the I2C_SAR byte (the device does not generate an interrupt at this point). After the next byte of the address (I2C_XSAR) is received, the I2C generates an interrupt and goes into SLAVE mode. Then I2C_SAR[2:1] are used as the upper 2 bits for the 10-bit extended address. The full 10-bit address is supplied by {I2C_SAR[2:1], I2C_XSAR[7:0]}. See Table 86.
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Table 86. I2C Slave Address Registers (I2C_SAR = 00C8h) Bit Reset CPU Access
Note: R/W = Read/Write.
7 0 R/W
6 0 R/W
5 0 R/W
4 0 R/W
3 0 R/W
2 0 R/W
1 0 R/W
0 0 R/W
Bit Position [7:1] SLA 0 GCE
Value Description 00h- 7Fh 0 1 7-bit slave address or upper 2 bits,I2C_SAR[2:1], of address when operating in 10-bit mode. I2C not enabled to recognize the General Call Address. I2C enabled to recognize the General Call Address.
I2C Extended Slave Address Register The I2C_XSAR register is used in conjunction with the I2C_SAR register to provide 10bit addressing of the I2C when in SLAVE mode. The I2C_SAR value forms the lower 8 bits of the 10-bit slave address. The full 10-bit address is supplied by {I2C_SAR[2:1], I2C_XSAR[7:0]}. When the register receives an address starting with F7h to F0h (I2C_SAR[7:3] = 11110b), the I2C recognizes that a 10-bit slave addressing mode is being selected. The I2C sends an ACK after receiving the I2C_XSAR byte (the device does not generate an interrupt at this point). After the next byte of the address (I2C_XSAR) is received, the I2C generates an interrupt and goes into SLAVE mode. Then I2C_SAR[2:1] are used as the upper 2 bits for the 10-bit extended address. The full 10-bit address is supplied by {I2C_SAR[2:1], I2C_XSAR[7:0]}. See Table 87.
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Table 87. I2C Extended Slave Address Registers (I2C_XSAR = 00C9h) Bit Reset CPU Access
Note: R/W = Read/Write.
7 0 R/W
6 0 R/W
5 0 R/W
4 0 R/W
3 0 R/W
2 0 R/W
1 0 R/W
0 0 R/W
Bit Position [7:0] SLAX
Value Description 00h- FFh Least-significant 8 bits of the 10-bit extended slave address.
I2C Data Register This register contains the data byte/slave address to be transmitted or the data byte just received. In transmit mode, the most-significant bit of the byte is transmitted first. In receive mode, the first bit received is placed in the most-significant bit of the register. After each byte is transmitted, the I2C_DR register contains the byte that is present on the bus in case a lost arbitration event occurs. See Table 88.
Table 88. I2C Data Registers (I2C_DR = 00CAh) Bit Reset CPU Access
Note: R/W = Read/Write.
7 0 R/W
6 0 R/W
5 0 R/W
4 0 R/W
3 0 R/W
2 0 R/W
1 0 R/W
0 0 R/W
Bit Position [7:0] DATA
Value Description 00h- FFh I2C data byte.
I2C Control Register The I2C_CTL register is a control register that is used to control the interrupts and the master slave relationships on the I2C bus. When the Interrupt Enable bit (IEN) is set to 1, the interrupt line goes High when the IFLG is set to 1. When IEN is cleared to 0, the interrupt line always remains Low. When the Bus Enable bit (ENAB) is set to 0, the I2C bus inputs SCLx and SDAx are ignored and the I2C module does not respond to any address on the bus. When ENAB is
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set to 1, the I2C responds to calls to its slave address and to the general call address if the GCE bit (I2C_SAR[0]) is set to 1. When the Master Mode Start bit (STA) is set to 1, the I2C enters MASTER mode and sends a START condition on the bus when the bus is free. If the STA bit is set to 1 when the I2C module is already in MASTER mode and one or more bytes are transmitted, then a repeated START condition is sent. If the STA bit is set to 1 when the I2C block is being accessed in SLAVE mode, the I2C completes the data transfer in SLAVE mode and then enters MASTER mode when the bus is released. The STA bit is automatically cleared after a START condition is set. Writing a 0 to this bit produces no effect. If the Master Mode Stop bit (STP) is set to 1 in MASTER mode, a STOP condition is transmitted on the I2C bus. If the STP bit is set to 1 in slave move, the I2C module operates as if a STOP condition is received, but no STOP condition is transmitted. If both STA and STP bits are set, the I2C block first transmits the STOP condition (if in MASTER mode) and then transmit the START condition. The STP bit is cleared automatically. Writing a 0 to this bit produces no effect. The I2C Interrupt Flag (IFLG) is set to 1 automatically when any of 30 of the possible 31 I2C states is entered. The only state that does not set the IFLG bit is state F8h. If IFLG is set to 1 and the IEN bit is also set, an interrupt is generated. When IFLG is set by the I2C, the Low period of the I2C bus clock line is stretched and the data transfer is suspended. When a 0 is written to IFLG, the interrupt is cleared and the I2C clock line is released. When the I2C Acknowledge bit (AAK) is set to 1, an Acknowledge is sent during the acknowledge clock pulse on the I2C bus if:
* * *
Either the whole of a 7-bit slave address or the first or second byte of a 10-bit slave address is received The general call address is received and the General Call Enable bit in I2C_SAR is set to 1 A data byte is received while in MASTER or SLAVE modes
When AAK is cleared to 0, a NACK is sent when a data byte is received in MASTER or SLAVE mode. If AAK is cleared to 0 in the Slave Transmitter mode, the byte in the I2C_DR register is assumed to be the final byte. After this byte is transmitted, the I2C block enter states C8h, then returns to the idle state. The I2C module does not respond to its slave address unless AAK is set. See Table 89.
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Table 89. I2C Control Registers (I2C_CTL = 00CBh) Bit Reset CPU Access 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R 0 0 R
Note: R/W = Read/Write; R = Read Only.
Bit Position 7 IEN 6 ENAB
Value Description 0 1 0 1 I2C interrupt is disabled. I2C interrupt is enabled. The I2C bus (SCL/SDA) is disabled and all inputs are ignored. The I2C bus (SCL/SDA) is enabled. Master mode START condition is sent. Master mode start-transmit START condition on the bus. Master mode STOP condition is sent. Master mode stop-transmit STOP condition on the bus. I2C interrupt flag is not set. I2C interrupt flag is set. Not Acknowledge. Acknowledge. Reserved.
5 STA 4 STP 3 IFLG 2 AAK [1:0]
0 1 0 1 0 1 0 1 00
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I2C Status Register The I2C_SR register is a Read Only register that contains a 5-bit status code in the five most-significant bits: the three least-significant bits are always 0. The Read Only I2C_SR registers share the same I/O addresses as the Write Only I2C_CCR registers. See Table 90.
Table 90. I2C Status Registers (I2C_SR = 00CCh) Bit Reset CPU Access
Note: R = Read only.
7 1 R
6 1 R
5 1 R
4 1 R
3 1 R
2 0 R
1 0 R
0 0 R
Bit Position [7:3] STAT [2:0]
Value 00000- 11111 000
Description 5-bit I2C status code. Reserved.
There are 29 possible status codes, as listed in Table 91. When the I2C_SR register contains the status code F8h, no relevant status information is available, no interrupt is generated and the IFLG bit in the I2C_CTL register is not set. All other status codes correspond to a defined state of the I2C. When each of these states is entered, the corresponding status code appears in this register and the IFLG bit in the I2C_CTL register is set. When the IFLG bit is cleared, the status code returns to F8h.
Table 91. I2C Status Codes Code 00h 08h 10h 18h 20h 28h 30h 38h 40h Status Bus error START condition transmitted Repeated START condition transmitted Address and Write bit transmitted, ACK received Address and Write bit transmitted, ACK not received Data byte transmitted in MASTER mode, ACK received Data byte transmitted in MASTER mode, ACK not received Arbitration lost in address or data byte Address and Read bit transmitted, ACK received
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Table 91. I2C Status Codes (Continued) Code 48h 50h 58h 60h 68h 70h 78h 80h 88h 90h 98h A0h A8h B0h B8h C0h C8h D0h D8h F8h Status Address and Read bit transmitted, ACK not received Data byte received in MASTER mode, ACK transmitted Data byte received in MASTER mode, NACK transmitted Slave address and Write bit received, ACK transmitted Arbitration lost in address as master, slave address and Write bit received, ACK transmitted General Call address received, ACK transmitted Arbitration lost in address as master, General Call address received, ACK transmitted Data byte received after slave address received, ACK transmitted Data byte received after slave address received, NACK transmitted Data byte received after General Call received, ACK transmitted Data byte received after General Call received, NACK transmitted STOP or repeated START condition received in SLAVE mode Slave address and Read bit received, ACK transmitted Arbitration lost in address as master, slave address and Read bit received, ACK transmitted Data byte transmitted in SLAVE mode, ACK received Data byte transmitted in SLAVE mode, ACK not received Last byte transmitted in SLAVE mode, ACK received Second Address byte and Write bit transmitted, ACK received Second Address byte and Write bit transmitted, ACK not received No relevant status information, IFLG = 0
If an illegal condition occurs on the I2C bus, the bus error state is entered (status code 00h). To recover from this state, the STP bit in the I2C_CTL register must be set and the IFLG bit cleared. The I2C then returns to the idle state. No STOP condition is transmitted on the I2C bus. Note: The STP and STA bits may be set to 1 at the same time to recover from the bus error. The I2C then sends a START condition.
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I2C Clock Control Register The I2C_CCR register is a Write Only register. The seven LSBs control the frequency at which the I2C bus is sampled and the frequency of the I2C clock line (SCL) when the I2C is in MASTER mode. The Write Only I2C_CCR registers share the same I/O addresses as the Read Only I2C_SR registers. See Table 92.
Table 92. I2C Clock Control Registers (I2C_CCR = 00CCh) Bit Reset CPU Access
Note: W = Read only.
7 0 W
6 0 W
5 0 W
4 0 W
3 0 W
2 0 W
1 0 W
0 0 W
Bit Position 7 [6:3] M [2:0] N
Value Description 0 Reserved. 0000- I2C clock divider scalar value. 1111 000- 111 I2C clock divider exponent.
The I2C clocks are derived from the CPU system clock. The frequency of the CPU system clock is fSCK. The I2C bus is sampled by the I2C block at the frequency fSAMP supplied by:
fSAMP = fSCLK 2N
In MASTER mode, the I2C clock output frequency on SCL (fSCL) is supplied by:
fSCL = fSCLK 10 * (M + 1)(2)N
The use of two separately-programmable dividers allows the MASTER mode output frequency to be set independently of the frequency at which the I2C bus is sampled. This feature is particularly useful in multimaster systems because the frequency at which the I2C bus is sampled must be at least 10 times the frequency of the fastest master on the bus to ensure that START and STOP conditions are always detected. By using two programmable clock divider stages, a high sampling frequency can be ensured while allowing the MASTER mode output to be set to a lower frequency.
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Bus Clock Speed The I2C bus is defined for bus clock speeds up to 100 KBPS (400 KBPS in FAST mode). To ensure correct detection of START and STOP conditions on the bus, the I2C must sample the I2C bus at least ten times faster than the bus clock speed of the fastest master on the bus. The sampling frequency should therefore be at least 1 MHz (4 MHz in FAST mode) to guarantee correct operation with other bus masters. The I2C sampling frequency is determined by the frequency of the CPU system clock and the value in the I2C_CCR bits 2 to 0. The bus clock speed generated by the I2C in MASTER mode is determined by the frequency of the input clock and the values in I2C_CCR[2:0] and I2C_CCR[6:3]. I2C Software Reset Register The I2C_SRR register is a Write Only register. Writing any value to this register performs a software reset of the I2C module. See Table 93.
Table 93. I2C Software Reset Register (I2C_SRR = 00CDh) Bit Reset CPU Access
Note: W = Write Only.
7 X W X W
6 X W
5 X W
4 X W
3 X W
2 X W
1 X W
0
Bit Position [7:0] SRR
Value Description 00h- FFh Writing any value to this register performs a software reset of the I2C module.
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ZiLOG Debug Interface
Introduction
The ZiLOG Debug Interface (ZDI) provides a built-in debugging interface to the eZ80(R) CPU. ZDI provides basic in-circuit emulation features including:
* * * * * * * * *
Examining and modifying internal registers Examining and modifying memory Starting and stopping the user program Setting program and data BREAK points Single-stepping the user program Executing user-supplied instructions Debugging the final product with the inclusion of one small connector Downloading code into SRAM C source-level debugging using ZiLOG Developer Studio (ZDS II)
The above features are built into the silicon. Control is provided via a two-wire interface that is connected to the ZPAK II Debug Interface Tool. Figure 36 illustrates a typical setup using a a target board, ZPAK II, and the host PC running ZiLOG Developer Studio. Refer to the ZiLOG website for more information about ZPAK II and ZDS II.
Target Board C O N N E C T O R
ZiLOG Developer Studio
ZPAK Emulator
eZ80 Product
Figure 36.Typical ZDI Debug Setup
ZDI allows reading and writing of most internal registers without disturbing the state of the machine. Reads and writes to memory may occur as fast as the ZDI can download and upload data, with a maximum frequency of one-half the CPU system clock frequency.
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Table 94 lists the recommended frequencies of the ZDI clock in relation to the system clock.
Table 94. Recommended ZDI Clock vs. System Clock Frequency System Clock Frequency 3-10 Mhz 8-16 Mhz 12-24 Mhz 20-50 Mhz ZDI Clock Frequency 1 Mhz 2 Mhz 4 Mhz 8 Mhz
ZDI-Supported Protocol
ZDI supports a bidirectional serial protocol. The protocol defines any device that sends data as the transmitter and any receiving device as the receiver. The device controlling the transfer is the master and the device being controlled is the slave. The master always initiates the data transfers and provides the clock for both receive and transmit operations. The ZDI block on the EZ80F92 device is considered a slave in all data transfers. Figure 37 illustrates the schematic for building a connector on a target board. This connector allows the user to connect directly to the ZPAK II debugger using a six-pin header.
TVDD (Target VDD )
10 K
10 K 2 1 3 5 4 6
EZ80F92 MCU
TCK (ZCL) TDI (ZDA)
6-Pin Target Connector
Figure 37.Schematic For Building a Target Board ZPAK II Connector
ZDI Clock and Data Conventions
The two pins used for communication with the ZDI block are the ZDI Clock pin (ZCL) and the ZDI Data pin (ZDA). On the EZ80F92 device, the ZCL pin is shared with the TCK pin while the ZDA pin is shared with the TDI pin. The ZCL and ZDA pin functions are
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only available when the On-Chip Instrumentation is disabled and the ZDI is therefore enabled. For general data communication, the data value on the ZDA pin can change only when ZCL is Low (0). The only exception is the ZDI START bit, which is indicated by a High-to-Low transition (falling edge) on the ZDA pin while ZCL is High. Data is shifted into and out of ZDI, with the most-significant bit (bit 7) of each byte being first in time, and the least-significant bit (bit 0) last in time. All information is passed between the master and the slave in 8-bit (single-byte) units. Each byte is transferred with nine clock cycles: eight to shift the data, and the ninth for internal operations.
ZDI START Condition
All ZDI commands are preceded by the ZDI START signal, which is a High-to-Low transition of ZDA when ZCL is High. The ZDI slave on the EZ80F92 device continually monitors the ZDA and ZCL lines for the START signal and does not respond to any command until this condition is met. The master pulls ZDA Low, with ZCL High, to indicate the beginning of a data transfer with the ZDI block. Figures 38 and 39 illustrate a valid ZDI START signal prior to writing and reading data, respectively. A Low-to-High transition of ZDA while the ZCL is High yields no effect. Data is shifted in during a Write to the ZDI block on the rising edge of ZCL, as illustrated in Figure 38. Data is shifted out during a Read from the ZDI block on the falling edge of ZCL as illustrated in Figure 39. When an operation is completed, the master stops during the ninth cycle and holds the ZCL signal High.
ZDI Data In (Write) ZDI Data In (Write)
ZCL
ZDA
Start Signal
Figure 38.ZDI Write Timing
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ZDI Data Out (Read)
ZDI Data Out (Read)
ZCL
ZDA
Start Signal
Figure 39.ZDI Read Timing
ZDI Single-Bit Byte Separator Following each 8-bit ZDI data transfer, a single-bit byte separator is used. To initiate a new ZDI command, the single-bit byte separator must be High (logical 1) to allow for a new ZDI START command to be sent. For all other cases, the single-bit byte separator can be either Low (logical 0) or High (logical 1). When ZDI is configured to allow the CPU to accept external bus requests, the single-bit byte separator should be Low (logical 0) during all ZDI commands. This Low value indicates that ZDI is still operating and is not ready to relinquish the Bus. The CPU does not accept the external bus requests until the single-bit byte separator is a High (logical 1). For more information about accepting bus requests in ZDI DEBUG mode, please see the Bus Requests During ZDI DEBUG Mode section on page 168.
ZDI Register Addressing
Following a START signal the ZDI master must output the ZDI register address. All data transfers with the ZDI block use special ZDI registers. The ZDI control registers that reside in the ZDI register address space should not be confused with the EZ80F92 device peripheral registers that reside in the I/O address space. Many locations in the ZDI control register address space are shared by two registers, one for Read Only access and one for Write Only access. As an example, a Read from ZDI register address 00h returns the eZ80 Product ID Low Byte while a Write to this same location, 00h, stores the Low byte of one of the address match values used for generating BREAK points. The format for a ZDI address is seven bits of address, followed by one bit for Read or Write control, and completed by a single-bit byte separator. The ZDI executes a Read or Write operation depending on the state of the R/W bit (0 = Write, 1 = Read). If no new START command is issued at completion of the Read or Write operation, the operation
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can be repeated. Repeated Read or Write operations can occur without requiring a resend of the ZDI command. To initiate a new ZDI command, a START signal must follow. Figure 40 illustrates the timing for address Writes to ZDI registers.
Single-Bit Byte Separator or new ZDI START Signal ZDI Address Byte ZCL S 1 2 3 4 5 6 7 8 9
ZDA
A6 msb
A5
A4
A3
A2
A1
A0 lsb
R/W
0/1
START Signal
0 = WRITE 1 = READ
Figure 40.ZDI Address Write Timing
ZDI Write Operations
ZDI Single-Byte Write For single-byte Write operations, the address and Write control bit are first written to the ZDI block. Following the single-bit byte separator, the data is shifted into the ZDI block on the next 8 rising edges of ZCL. The master terminates activity after 8 clock cycles.Figure 41 illustrates the timing for ZDI single-byte Write operations.
ZDI Data Byte ZCL 7 8 9 1 2 3 4 5 6 7 8 9
ZDA
A0
Write
0/1
D7 msb of DATA
D6
D5
D4
D3
D2
D1
D0 lsb of DATA
1
lsb of ZDI Address
Single-Bit Byte Separator
End of Data or New ZDI START Signal
Figure 41.ZDI Single-Byte Data Write Timing
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ZDI Block Write The Block Write operation is initiated in the same manner as the single-byte Write operation, but instead of terminating the Write operation after the first data byte is transferred, the ZDI master can continue to transmit additional bytes of data to the ZDI slave on the EZ80F92 device. After the receipt of each byte of data the ZDI register address increments by 1. If the ZDI register address reaches the end of the Write Only ZDI register address space (30h), the address stops incrementing. Figure 42 illustrates the timing for ZDI Block Write operations.
ZDI Data Bytes ZCL 7 8 9 1 2 3 7 8 9 1 2 9
ZDA
A0
Write
0/1
D7 msb of DATA Byte 1
D6
D5
D1
D0 lsb of DATA Byte 1
0/1
D7
D6 msb of DATA Byte 2
1
lsb of ZDI Address
Single-Bit Byte Separator
Single-Bit Byte Separator
Figure 42.ZDI Block Data Write Timing
ZDI Read Operations
ZDI Single-Byte Read Single-byte Read operations are initiated in the same manner as single-byte Write operations, with the exception that the R/W bit of the ZDI register address is set to 1. Upon receipt of a slave address with the R/W bit set to 1, the EZ80F92 device's ZDI block loads the selected data into the shifter at the beginning of the first cycle following the single-bit data separator. The most-significant bit (msb) is shifted out first. Figure 43 illustrates the timing for ZDI single-byte Read operations.
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ZDI Data Byte ZCL 7 8 9 1 2 3 4 5 6 7 8 9
ZDA
A0
Read
0/1
D7 msb of DATA
D6
D5
D4
D3
D2
D1
D0 lsb of DATA
1
lsb of ZDI Address
Single-Bit Byte Separator
End of Data or New ZDI START Signal
Figure 43.ZDI Single-Byte Data Read Timing
ZDI Block Read A Block Read operation is initiated the same as a single-byte Read; however, the ZDI master continues to clock in the next byte from the ZDI slave as the ZDI slave continues to output data. The ZDI register address counter increments with each Read. If the ZDI register address reaches the end of the Read Only ZDI register address space (20h), the address stops incrementing. Figure 44 illustrates the ZDI's Block Read timing.
ZDI Data Bytes ZCL 7 8 9 1 2 3 7 8 9 1 2 9
ZDA
A0
Read
0/1
D7 msb of DATA Byte 1
D6
D5
D1
D0 lsb of DATA Byte 1
0/1
D7 msb of DATA Byte 2
D6
1
lsb of ZDI Address
Single-Bit Byte Separator
Single-Bit Byte Separator
Figure 44.ZDI Block Data Read Timing
Operation of the EZ80F92 Device During ZDI Breakpoints
If the ZDI forces the CPU to BREAK, only the CPU suspends operation. The system clock continues to operate and drive other peripherals. Those peripherals that can operate autonomously from the CPU may continue to operate, if so enabled. For example, the Watch-Dog Timer and Programmable Reload Timers continue to count during a ZDI BREAK point.
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When using the ZDI interface, any Write or Read operations of peripheral registers in the I/O address space produces the same effect as Read or Write operations using the CPU. Because many register Read/Write operations exhibit secondary effects, such as clearing flags or causing operations to commence, the effects of the Read/Write operations during a ZDI BREAK must be taken into consideration.
Bus Requests During ZDI DEBUG Mode
The ZDI block on the EZ80F92 device allows an external device to take control of the address and data bus while the EZ80F92 device is in DEBUG mode. ZDI_BUSACK_EN causes ZDI to allow or prevent acknowledgement of bus requests by external peripherals. The bus acknowledge only occurs at the end of the current ZDI operation (indicated by a High during the single-bit byte separator). The default reset condition is for bus acknowledgement to be disabled. To allow bus acknowledgement, the ZDI_BUSACK_EN must be written. When an external bus request (BUSREQ pin asserted) is detected, ZDI waits until completion of the current operation before responding. ZDI acknowledges the bus request by asserting the bus acknowledge (BUSACK) signal. If the ZDI block is not currently shifting data, it acknowledges the bus request immediately. ZDI uses the single-bit byte separator of each data word to determine if it is at the end of a ZDI operation. If the bit is a logical 0, ZDI does not assert BUSACK to allow additional data Read or Write operations. If the bit is a logical 1, indicating completion of the ZDI commands, BUSACK is asserted. Potential Hazards of Enabling Bus Requests During DEBUG Mode There are some potential hazards that the user must be aware of when enabling external bus requests during ZDI DEBUG mode. First, when the address and data bus are being used by an external source, ZDI must only access ZDI registers and internal CPU registers to prevent possible Bus contention. The bus acknowledge status is reported in the ZDI_BUS_STAT register. The BUSACK output pin also indicates the bus acknowledge state. A second hazard is that when a bus acknowledge is granted, the ZDI is subject to any WAIT states that are assigned to the device currently being accessed by the external peripheral. To prevent data errors, ZDI should avoid data transmission while another device is controlling the bus. Finally, exiting ZDI DEBUG mode while an external peripheral controls the address and data buses, as indicated by BUSACK assertion, may produce unpredictable results.
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ZDI Write Only Registers
Table 95 lists the ZDI Write Only registers. Many of the ZDI Write Only addresses are shared with ZDI Read Only registers.
Table 95. ZDI Write Only Registers ZDI Address 00h 01h 02h 04h 05h 06h 08h 09h 0Ah 0Ch 0Dh 0Eh 10h 11h 13h 14h 15h 16h 17h 21h 22h 23h 24h 25h 30h Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh 00h 00h XXh XXh XXh 00h 00h XXh XXh XXh XXh XXh XXh
ZDI Register Name ZDI_ADDR0_L ZDI_ADDR0_H ZDI_ADDR0_U ZDI_ADDR1_L ZDI_ADDR1_H ZDI_ADDR1_U ZDI_ADDR2_L ZDI_ADDR2_H ZDI_ADDR2_U ZDI_ADDR3_L ZDI_ADDR3_H ZDI_ADDR3_U ZDI_BRK_CTL ZDI_MASTER_CTL ZDI_WR_DATA_L ZDI_WR_DATA_H ZDI_WR_DATA_U ZDI_RW_CTL ZDI_BUS_CTL ZDI_IS4 ZDI_IS3 ZDI_IS2 ZDI_IS1 ZDI_IS0 ZDI_WR_MEM
ZDI Register Function Address Match 0 Low Byte Address Match 0 High Byte Address Match 0 Upper Byte Address Match 1 Low Byte Address Match 1 High Byte Address Match 1 Upper Byte Address Match 2 Low Byte Address Match 2 High Byte Address Match 2 Upper Byte Address Match 3 Low Byte Address Match 3 High Byte Address Match 4 Upper Byte BREAK Control register Master Control register Write Data Low Byte Write Data High Byte Write Data Upper Byte Read/Write Control register Bus Control register Instruction Store 4 Instruction Store 3 Instruction Store 2 Instruction Store 1 Instruction Store 0 Write Memory register
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ZDI Read Only Registers
Table 96 lists the ZDI Read Only registers. Many of the ZDI Read Only addresses are shared with ZDI Write Only registers.
Table 96. ZDI Read Only Registers ZDI Address 00h 01h 02h 03h 10h 11h 12h 17h 20h Reset Value 07h 00h XXh 00h XXh XXh XXh 00h XXh
ZDI Register Name ZDI_ID_L ZDI_ID_H ZDI_ID_REV ZDI_STAT ZDI_RD_L ZDI_RD_H ZDI_RD_U ZDI_BUS_STAT ZDI_RD_MEM
ZDI Register Function eZ80 Product ID Low Byte register eZ80 Product ID High Byte register eZ80 Product ID Revision register Status register Read Memory Address Low Byte register Read Memory Address High Byte register Read Memory Address Upper Byte register Bus Status register Read Memory Data Value
ZDI Register Definitions
ZDI Address Match Registers The four sets of address match registers are used for setting the addresses for generating BREAK points. When the accompanying BRK_ADDRX bit is set in the ZDI BREAK Control register to enable the particular address match, the current EZ80F92 address is compared with the 3-byte address set, {ZDI_ADDRx_U, ZDI_ADDRx_H, ZDI_ADDR_x_L}. If the CPU is operating in ADL mode, the address is supplied by ADDR[23:0]. If the CPU is operating in Z80 mode, the address is supplied by {MBASE[7:0], ADDR[15:0]}. If a match is found, ZDI issues a BREAK to the EZ80F92 device placing the processor in ZDI mode pending further instructions from the ZDI interface block. If the address is not the first op-code fetch, the ZDI BREAK is executed at the end of the instruction in which it is executed. There are four sets of address match registers. They can be used in conjunction with each other to BREAK on branching instructions. See Table 97.
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Table 97. ZDI Address Match Registers (ZDI_ADDR0_L = 00h, ZDI_ADDR0_H = 01h, ZDI_ADDR0_U = 02h, ZDI_ADDR1_L = 04h, ZDI_ADDR1_H = 05h, ZDI_ADDR1_U = 06h, ZDI_ADDR2_L = 08h, ZDI_ADDR2_H = 09h, ZDI_ADDR2_U = 0Ah, ZDI_ADDR3_L = 0Ch, ZDI_ADDR3_H = 0Dh, and ZDI_ADDR3_U = 0Eh in the ZDI Register Write Only Address Space) Bit Reset CPU Access
Note: W = Write Only.
7 X W
6 X W
5 X W
4 X W
3 X W
2 X W
1 X W
0 X W
Bit Position [7:0] ZDI_ADDRx_L, ZDI_ADDRx_H, or ZDI_ADDRx_U
Value Description 00h- FFh The four sets of ZDI address match registers are used for setting the addresses for generating BREAK points. The 24-bit addresses are supplied by {ZDI_ADDRx_U, ZDI_ADDRx_H, ZDI_ADDRx_L, where x is 0, 1, 2, or 3.
ZDI BREAK Control Register The ZDI BREAK Control register is used to enable BREAK points. ZDI asserts a BREAK when the CPU instruction address, ADDR[23:0], matches the value in the ZDI Address Match 3 registers, {ZDI_ADDR3_U, ZDI_ADDR3_H, ZDI_ADDR3_L}. BREAKs can only occur on an instruction boundary. If the instruction address is not the beginning of an instruction (that is, for multibyte instructions), then the BREAK occurs at the end of the current instruction. The BRK_NEXT bit is set to 1. The BRK_NEXT bit must be reset to 0 to release the BREAK. See Table 98.
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Table 98. ZDI BREAK Control Register (ZDI_BRK_CTL = 10h in the ZDI Write Only Register Address Space) Bit Reset CPU Access
Note: W = Write Only.
7 0 W
6 0 W
5 0 W
4 0 W
3 0 W
2 0 W
1 0 W
0 0 W
Bit Position 7 brk_next
Value Description 0 The ZDI BREAK on the next CPU instruction is disabled. Clearing this bit releases the CPU from its current BREAK condition. The ZDI BREAK on the next CPU instruction is enabled. The CPU can use multibyte Op Codes and multibyte operands. BREAK points only occur on the first Op Code in a multibyte Op Code instruction. If the ZCL pin is High and the ZDA pin is Low at the end of RESET, this bit is set to 1 and a BREAK occurs on the first instruction following the RESET. This bit is set automatically during ZDI BREAK on address match. A BREAK can also be forced by writing a 1 to this bit. The ZDI BREAK, upon matching BREAK address 3, is disabled. The ZDI BREAK, upon matching BREAK address 3, is enabled. The ZDI BREAK, upon matching BREAK address 2, is disabled. The ZDI BREAK, upon matching BREAK address 2, is enabled. The ZDI BREAK, upon matching BREAK address 1, is disabled. The ZDI BREAK, upon matching BREAK address 1, is enabled. The ZDI BREAK, upon matching BREAK address 0, is disabled. The ZDI BREAK, upon matching BREAK address 0, is enabled.
1
6 brk_addr3
0 1
5 brk_addr2
0 1
4 brk_addr1
0 1
3 brk_addr0
0 1
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Bit Position 2 ign_low_1
Value Description 0 The Ignore the Low Byte function of the ZDI Address Match 1 registers is disabled. If BRK_ADDR1 is set to 1, ZDI initiates a BREAK when the entire 24-bit address, ADDR[23:0], matches the 3-byte value {ZDI_ADDR1_U, ZDI_ADDR1_H, ZDI_ADDR1_L}. The Ignore the Low Byte function of the ZDI Address Match 1 registers is enabled. If BRK_ADDR1 is set to 1, ZDI initiates a BREAK when only the upper 2 bytes of the 24-bit address, ADDR[23:8], match the 2-byte value {ZDI_ADDR1_U, ZDI_ADDR1_H}. As a result, a BREAK can occur anywhere within a 256-byte page. The Ignore the Low Byte function of the ZDI Address Match 1 registers is disabled. If BRK_ADDR0 is set to 1, ZDI initiates a BREAK when the entire 24-bit address, ADDR[23:0], matches the 3-byte value {ZDI_ADDR0_U, ZDI_ADDR0_H, ZDI_ADDR0_L}. The Ignore the Low Byte function of the ZDI Address Match 1 registers is enabled. If the BRK_ADDR1 is set to 0, ZDI initiates a BREAK when only the upper 2 bytes of the 24-bit address, ADDR[23:8], match the 2 bytes value {ZDI_ADDR0_U, ZDI_ADDR0_H}. As a result, a BREAK can occur anywhere within a 256-byte page. ZDI SINGLE STEP mode is disabled. ZDI SINGLE STEP mode is enabled. ZDI asserts a BREAK following execution of each instruction.
1
1 ign_low_0
0
1
0 single_step
0 1
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ZDI Master Control Register The ZDI Master Control register provides control of the EZ80F92 device. It is capable of forcing a RESET and waking up the EZ80F92 device from the low-power modes (HALT or SLEEP). See Table 99.
Table 99. ZDI Master Control Register (ZDI_MASTER_CTL = 11h in ZDI Register Write Address Spaces) Bit Reset CPU Access
Note: W = Write Only.
7 0 W
6 0 W
5 0 W
4 0 W
3 0 W
2 0 W
1 0 W
0 0 W
Bit Position 7 ZDI_RESET
Value 0 1
Description No action. Initiate a RESET of the CPU. This bit is automatically cleared at the end of the RESET event.
[6:0]
0000000 Reserved.
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ZDI Write Data Registers These three registers are used in the ZDI Write Only register address space to store the data that is written when a Write instruction is sent to the ZDI Read/Write Control register (ZDI_RW_CTL). The ZDI Read/Write Control register is located at ZDI address 16h immediately following the ZDI Write Data registers. As a result, the ZDI Master is allowed to write the data to {ZDI_WR_U, ZDI_WR_H, ZDI_WR_L} and the Write command in one data transfer operation. See Table 100.
Table 100. ZDI Write Data Registers (ZDI_WR_U = 13h, ZDI_WR_H = 14h, and ZDI_WR_L = 15h in the ZDI Register Write Only Address Space) Bit Reset CPU Access 7 X W 6 X W 5 X W 4 X W 3 X W 2 X W 1 X W 0 X W
Note: X = Undefined; W = Write.
Bit Position [7:0] ZDI_WR_L, ZDI_WR_H, or ZDI_WR_L
Value Description 00h- FFh These registers contain the data that is written during execution of a Write operation defined by the ZDI_RW_CTL register. The 24-bit data value is stored as {ZDI_WR_U, ZDI_WR_H, ZDI_WR_L}. If less than 24 bits of data are required to complete the required operation, the data is taken from the least-significant byte(s).
ZDI Read/Write Control Register The ZDI Read/Write Control register is used in the ZDI Write Only Register address to read data from, write data to, and manipulate the CPU's registers or memory locations. When this register is written, the EZ80F92 device immediately performs the operation corresponding to the data value written as described in Table 101. When a Read operation is executed via this register, the requested data values are placed in the ZDI Read Data registers {ZDI_RD_U, ZDI_RD_H, ZDI_RD_L}. When a Write operation is executed via this register, the Write data is taken from the ZDI Write Data registers {ZDI_WR_U, ZDI_WR_H, ZDI_WR_L}. See Table 101. Refer to the eZ80 CPU User Manual (UM0077) for information regarding the CPU registers.
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Table 101. ZDI Read/Write Control Register Functions (ZDI_RW_CTL = 16h in the ZDI Register Write Only Address Space ) Hex Value 00 Hex Value 80
Command Read {MBASE, A, F} ZDI_RD_U MBASE ZDI_RD_H F ZDI_RD_L A Read BC ZDI_RD_U BCU ZDI_RD_H B ZDI_RD_L C Read DE ZDI_RD_U DEU ZDI_RD_H D ZDI_RD_L E Read HL ZDI_RD_U HLU ZDI_RD_H H ZDI_RD_L L Read IX ZDI_RD_U IXU ZDI_RD_H IXH ZDI_RD_L IXL Read IY ZDI_RD_U IYU ZDI_RD_H IYH ZDI_RD_L IYL Read SP In ADL mode, SP = SPL. In Z80 mode, SP = SPS. Read PC ZDI_RD_U PC[23:16] ZDI_RD_H PC[15:8] ZDI_RD_L PC[7:0] Set ADL ADL 1
Command Write AF MBASE ZDI_WR_U F ZDI_WR_H A ZDI_WR_L Write BC BCU ZDI_WR_U B ZDI_WR_H C ZDI_WR_L Write DE DEU ZDI_WR_U D ZDI_WR_H E ZDI_WR_L Write HL HLU ZDI_WR_U H ZDI_WR_H L ZDI_WR_L Write IX IXU ZDI_WR_U IXH ZDI_WR_H IXL ZDI_WR_L Write IY IYU ZDI_WR_U IYH ZDI_WR_H IYL ZDI_WR_L Write SP In ADL mode, SP = SPL. In Z80 mode, SP = SPS. Write PC PC[23:16] ZDI_WR_U PC[15:8] ZDI_WR_H PC[7:0] ZDI_WR_L Reserved
01
81
02
82
03
83
04
84
05
85
06
86
07
87
08
88
The eZ80(R) CPU's alternate register set (A', F', B', C', D', E', HL') cannot be read directly. The ZDI programmer must execute the exchange instruction (EXX) to gain access to the alternate eZ80(R) CPU register set.
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Table 101. ZDI Read/Write Control Register Functions (ZDI_RW_CTL = 16h in the ZDI Register Write Only Address Space (Continued)) Hex Value 09 0A Hex Value 89 8A
Command Reset ADL ADL 0 Exchange CPU register sets AF AF' BC BC' DE DE' HL HL' Read memory from current PC value, increment PC
Command Reserved Reserved
0B
8B
Write memory from current PC value, increment PC
The eZ80(R) CPU's alternate register set (A', F', B', C', D', E', HL') cannot be read directly. The ZDI programmer must execute the exchange instruction (EXX) to gain access to the alternate eZ80(R) CPU register set.
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ZDI Bus Control Register The ZDI Bus Control register controls bus requests during DEBUG mode. It enables or disables bus acknowledge in ZDI DEBUG mode and allows ZDI to force assertion of the BUSACK signal. This register should only be written during ZDI DEBUG mode (that is, following a BREAK). See Table 102.
Table 102. ZDI Bus Control Register (ZDI_BUS_CTL = 17h in the ZDI Register Write Only Address Space) Bit Reset CPU Access
Note: W = Write Only.
7 0 W
6 0 W
5 0 W
4 0 W
3 0 W
2 0 W
1 0 W
0 0 W
Bit Position 7 ZDI_BUSAK_EN
Value 0
Description Bus requests by external peripherals using the BUSREQ pin are ignored. The bus acknowledge signal, BUSACK, is not asserted in response to any bus requests. Bus requests by external peripherals using the BUSREQ pin are accepted. A bus acknowledge occurs at the end of the current ZDI operation. The bus acknowledge is indicated by asserting the BUSACK pin in response to a bus request. Deassert the bus acknowledge pin (BUSACK) to return control of the address and data buses back to ZDI. Assert the bus acknowledge pin (BUSACK) to pass control of the address and data buses to an external peripheral. Reserved.
1
6 ZDI_BUSAK
0 1
[5:0]
000000
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Instruction Store 4:0 Registers The ZDI Instruction Store registers are located in the ZDI Register Write Only address space. They can be written with instruction data for direct execution by the CPU. When the ZDI_IS0 register is written, the EZ80F92 device exits the ZDI BREAK state and executes a single instruction. The Op Codes and operands for the instruction come from these Instruction Store registers. The Instruction Store Register 0 is the first byte fetched, followed by Instruction Store registers 1, 2, 3, and 4, as necessary. Only the bytes the processor requires to execute the instruction must be stored in these registers. Some CPU instructions, when combined with the MEMORY mode suffixes (.SIS, .SIL, .LIS, or .LIL), require 6 bytes to operate. These 6-byte instructions cannot be executed directly using the ZDI Instruction Store registers. See Table 103. Note: The Instruction Store 0 register is located at a higher ZDI address than the other Instruction Store registers. This feature allows the use of the ZDI auto-address increment function to load and execute a multibyte instruction with a single data stream from the ZDI master. Execution of the instruction commences with writing the most recent byte to ZDI_IS0.
Table 103. Instruction Store 4:0 Registers (ZDI_IS4 = 21h, ZDI_IS3 = 22h, ZDI_IS2 = 23h, ZDI_IS1 = 24h, and ZDI_IS0 = 25h in the ZDI Register Write Only Address Space) Bit Reset CPU Access 7 X W 6 X W 5 X W 4 X W 3 X W 2 X W 1 X W 0 X W
Note: X = Undefined; W = Write.
Bit Position [7:0] ZDI_IS4, ZDI_IS3, ZDI_IS2, ZDI_IS1, or ZDI_IS0
Value Description 00h- FFh These registers contain the Op Codes and operands for immediate execution by the CPU following a Write to ZDI_IS0. The ZDI_IS0 register contains the first Op Code of the instruction. The remaining ZDI_ISx registers contain any additional Op Codes or operand dates required for execution of the required instruction.
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ZDI Write Memory Register A Write to the ZDI Write Memory register causes the EZ80F92 device to write the 8-bit data to the memory location specified by the current address in the program counter. In Z80 MEMORY mode, this address is {MBASE, PC[15:0]}. In ADL MEMORY mode, this address is PC[23:0]. The program counter, PC, increments after each data Write. However, the ZDI register address does not increment automatically when this register is accessed. As a result, the ZDI master is allowed to write any number of data bytes by writing to this address one time followed by any number of data bytes. See Table 104.
Table 104. ZDI Write Memory Register (ZDI_WR_MEM = 30h in the ZDI Register Write Only Address Space) Bit Reset CPU Access 7 X W 6 X W 5 X W 4 X W 3 X W 2 X W 1 X W 0 X W
Note: X = Undefined; W = Write.
Bit Position [7:0] ZDI_WR_MEM
Value Description 00h- FFh The 8-bit data that is transferred to the ZDI slave following a Write to this address is written to the address indicated by the current program counter. The program counter is incremented following each 8 bits of data. In Z80 MEMORY mode, ({MBASE, PC[15:0]}) 8 bits of transferred data. In ADL MEMORY mode, (PC[23:0]) 8-bits of transferred data.
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eZ80 Product ID Low and High Byte Registers The eZ80 Product ID Low and High Byte registers combine to provide a means for an external device to determine the particular eZ80Acclaim!TM product being addressed. See Tables 105 and 106.
Table 105. eZ80 Product ID Low Byte Register (ZDI_ID_L = 00h in the ZDI Register Read Only Address Space) Bit Reset CPU Access
Note: R = Read Only.
7 0 R
6 0 R
5 0 R
4 0 R
3 0 R
2 1 R
1 1 R
0 1 R
Bit Position [7:0] ZDI_ID_L
Value Description 07h {ZDI_ID_H, ZDI_ID_L} = {00h, 07h} indicates the EZ80F92 product.
Table 106. eZ80 Product ID High Byte Register (ZDI_ID_H = 01h in the ZDI Register Read Only Address Space) Bit Reset CPU Access
Note: R = Read Only.
7 0 R
6 0 R
5 0 R
4 0 R
3 0 R
2 0 R
1 0 R
0 0 R
Bit Position [7:0] ZDI_ID_H
Value Description 00h {ZDI_ID_H, ZDI_ID_L} = {00h, 07h} indicates the EZ80F92 product.
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eZ80 Product ID Revision Register The eZ80 Product ID Revision register identifies the current revision of the EZ80F92 product. See Table 107.
Table 107. eZ80 Product ID Revision Register (ZDI_ID_REV = 02h in the ZDI Register Read Only Address Space) Bit Reset CPU Access 7 X R 6 X R 5 X R 4 X R 3 X R 2 X R 1 X R 0 X R
Note: X = Undetermined; R = Read Only.
Bit Position [7:0] ZDI_ID_REV
Value Description 00h- FFh Identifies the current revision of the EZ80F92 product.
ZDI Status Register The ZDI Status register provides current information about the EZ80F92 device. See Table 108.
Table 108. ZDI Status Register (ZDI_STAT = 03h in the ZDI Register Read Only Address Space) Bit Reset CPU Access
Note: R = Read Only.
7 0 R
6 0 R
5 0 R
4 0 R
3 0 R
2 0 R
1 0 R
0 0 R
Bit Position 7 ZDI_ACTIVE 6 5 HALT_SLP
Value Description 0 1 0 0 1 The CPU is not functioning in ZDI mode. The CPU is currently functioning in ZDI mode. Reserved. The CPU is not currently in HALT or SLEEP mode. The CPU is currently in HALT or SLEEP mode.
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Bit Position 4 ADL
Value Description 0 1 The CPU is operating in Z80 MEMORY mode. (ADL bit = 0) The CPU is operating in ADL MEMORY mode. (ADL bit = 1) The CPU's Mixed-Memory mode (MADL) bit is reset to 0. The CPU's Mixed-Memory mode (MADL) bit is set to 1. The CPU's Interrupt Enable Flag 1 is reset to 0. Maskable interrupts are disabled. The CPU's Interrupt Enable Flag 1 is set to 1. Maskable interrupts are enabled. Reserved.
3 MADL 2 IEF1
0 1 0 1
[1:0]
00
ZDI Read Register Low, High, and Upper The ZDI register Read Only address space offers Low, High, and Upper functions, which contain the value read by a Read operation from the ZDI Read/Write Control register (ZDI_RW_CTL). This data is valid only while in ZDI BREAK mode and only if the instruction is read by a request from the ZDI Read/Write Control register. See Table 109.
Table 109. ZDI Read Register Low, High and Upper (ZDI_RD_L = 10h, ZDI_RD_H = 11h, and ZDI_RD_U = 12h in the ZDI Register Read Only Address Space) Bit Reset CPU Access
Note: R = Read Only.
7 0 R
6 0 R
5 0 R
4 0 R
3 0 R
2 0 R
1 0 R
0 0 R
Bit Position [7:0] ZDI_RD_L, ZDI_RD_H, or ZDI_RD_U
Value Description 00h- FFh Values read from the memory location as requested by the ZDI Read Control register during a ZDI Read operation. The 24-bit value is supplied by {ZDI_RD_U, ZDI_RD_H, ZDI_RD_L}.
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ZDI Bus Status Register The ZDI Bus Status register monitors BUSACKs during ZDI DEBUG mode. See Table 110.
Table 110. ZDI Bus Control Register (ZDI_BUS_STAT = 17h in the ZDI Register Read Only Address Space) Bit Reset CPU Access
Note: R = Read Only.
7 0 R
6 0 R
5 0 R
4 0 R
3 0 R
2 0 R
1 0 R
0 0 R
Bit Position 7 ZDI_BUSACK_EN
Value 0
Description Bus requests by external peripherals using the BUSREQ pin are ignored. The bus acknowledge signal, BUSACK, is not asserted. Bus requests by external peripherals using the BUSREQ pin are accepted. A bus acknowledge occurs at the end of the current ZDI operation. The bus acknowledge is indicated by asserting the BUSACK pin. Address and data buses are not relinquished to an external peripheral. bus acknowledge is deasserted (BUSACK pin is High). Address and data buses are relinquished to an external peripheral. bus acknowledge is asserted (BUSACK pin is Low). Reserved.
1
6 ZDI_BUS_STAT
0
1
[5:0]
000000
ZDI Read Memory Register When a Read is executed from the ZDI Read Memory register, the EZ80F92 device fetches the data from the memory address currently pointed to by the program counter, PC; the program counter is then incremented. In Z80 MEMORY mode, the memory address is {MBASE, PC[15:0]}. In ADL MEMORY mode, the memory address is PC[23:0]. Refer to the eZ80 CPU User Manual (UM0077) for more information regarding Z80 and ADL MEMORY modes. The program counter, PC, increments after each data Read. However, the ZDI register address does not increment automatically when this register is accessed. As a result, the ZDI master can read any number of data bytes out of memory through the ZDI Read Memory register. See Table 111.
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Table 111. ZDI Read Memory Register (ZDI_RD_MEM = 20h in the ZDI Register Read Only Address Space) Bit Reset CPU Access
Note: R = Read Only.
7 0 R
6 0 R
5 0 R
4 0 R
3 0 R
2 0 R
1 0 R
0 0 R
Bit Position [7:0] ZDI_RD_MEM
Value Description 00h- FFh 8-bit data read from the memory address indicated by the CPU's program counter. In Z80 MEMORY mode, 8-bit data is transferred out from address {MBASE, PC[15:0]}. In ADL Memory mode, 8-bit data is transferred out from address PC[23:0].
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On-Chip Instrumentation
Introduction to On-Chip Instrumentation
On-Chip Instrumentation1 (OCITM) for the eZ80(R) CPU core enables powerful debugging features. The OCI provides run control, memory and register visibility, complex breakpoints, and trace history features. The OCI employs all of the functions of the ZiLOG Debug Interface (ZDI) as described in the ZiLOG Debug Interface section that starts on page 161. It also adds the following debug features:
* * *
Control via a 4-pin Joint Test Action Group (JTAG)-standard port that conforms to the IEEE Standard 1149.1 (Test Access Port and Boundary Scan Architecture)2 Complex break point trigger functions Break point enhancements, such as the ability to: - Define two break point addresses that form a range - Break on masked data values - Start or stop trace - Assert a trigger output signal Trace history buffer Software break point instruction
* * * * * *
There are four sections to the OCI: JTAG interface ZDI debug control Trace buffer memory Complex triggers
OCI Activation
OCI features clock initialization circuitry so that external debug hardware can be detected during power-up. The external debugger must drive the OCI clock pin (TCK) Low at least two system clock cycles prior to the end of the RESET to activate the OCI block. If TCK is High at the end of the RESET, the OCI block shuts down so that it does not draw power in normal product operation. When the OCI is shut down, ZDI is enabled directly and can
1. On-Chip Instrumentation and OCI are trademarks of First Silicon Solutions, Inc. 2. The EZ80F92 does not contain the boundary scan register required for 1149.1 compliance.
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be accessed via the clock (TCK) and data (TDI) pins. See the ZiLOG Debug Interface section on page 161 for more information about ZDI.
OCI Interface
There are five dedicated pins on the EZ80F92 device for the OCI interface. Four pins-- TCK, TMS, TDI, and TDO--are required for IEEE Standard 1149.1-compliant JTAG ports. The TRIGOUT pin provides additional testability features. These five OCI pins are described in Table 112.
Table 112. OCI Pins Symbol TCK Name Clock. Type Input Description Asynchronous to the primary CPU system clock. The TCK period must be at least twice the system clock period. During RESET, this pin is sampled to select either OCI or ZDI DEBUG modes. If Low during RESET, the OCI is enabled. If High during RESET, the OCI is powered down and ZDI DEBUG mode is enabled. When ZDI DEBUG mode is active, this pin is the ZDI clock. On-chip pull-up ensures a default value of 1 (High). This serial test mode input controls JTAG mode selection. On-chip pull-up ensures a default value of 1 (High). The TMS signal is sampled on the rising edge of the TCK signal. Serial test data input. On-chip pull-up ensures a default value of 1 (High). This pin is input-only when the OCI is enabled. The input data is sampled on the rising edge of the TCK signal. When the OCI is disabled, this pin functions as the ZDA (ZDI Data) I/O pin. The output data changes on the falling edge of the TCK signal. Generates an active High trigger pulse when valid OCI trigger events occur. Output is tristate when no data is being driven out.
TMS
Test Mode Select
Input
TDI
Data In
Input (OCI enabled)
I/O (OCI disabled) TDO TRIGOUT Data Out Trigger Output Output Output
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OCI Information Requests
For additional information regarding On-Chip Instrumentation, or to order OCI debug tools, please contact:
First Silicon Solutions, Inc. 5440 SW Westgate Drive, Suite 240 Portland, OR 97221 Phone: (503) 292-6730 Fax: (503) 292-5840
www.fs2.com
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Random Access Memory
The EZ80F92 features 8 KB (8192 bytes) single-port data Random Access Memory (RAM) for general-purpose use. The eZ80F93 features 4KB (4096 bytes) general-purpose RAM. RAM can be enabled or disabled, and it can be relocated to the top of any 64 KB page in memory. Data is passed to and from RAM via the 8-bit data bus. On-chip RAM operates with zero WAIT states. For the EZ80F92, RAM occupies memory addresses in the range {RAM_ADDR_U[7:0], E000h} to {RAM_ADDR_U[7:0], FFFFh}. Following a RESET, RAM is enabled with RAM_ADDR_U set to FFh. Figure 45 illustrates a memory map of on-chip RAM. In this example, the RAM Address Upper Byte register, RAM_ADDR_U, is set to 7Ah. Figure 45 is not drawn to scale, as RAM occupies only a very small fraction of the available 16 MB address space.
Memory Location FFFFFFh
7AFFFFh 8KB General Purpose RAM 7AE000h RAM_ADDR_U 7Ah
000000h
Figure 45.EZ80F92 On-Chip RAM Memory Addressing Example
For the eZ80F93 device, RAM occupies memory addresses in the range {RAM_ADDR_U[7:0], F000h} to {RAM_ADDR_U[7:0], F000h}. Following a RESET, RAM is enabled with RAM_ADDR_U set to FFh. Figure 46 illustrates a memory map of on-chip RAM. In this example, the RAM Address Upper Byte register, RAM_ADDR_U, is set to 7Ah. Figure 45 is not drawn to scale, as RAM occupies only a very small fraction of the available 16 MB address space.
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Memory Location FFFFFFh
7AFFFFh 4KB General Purpose RAM 7AF000h RAM_ADDR_U 7Ah
000000h
Figure 46.eZ80F93 On-Chip RAM Memory Addressing Example
When enabled, on-chip RAM assumes priority over on-chip Flash Memory and any Memory Chip Selects that can also be enabled in the same address space. If an address is generated in a range that is covered by both the RAM address space and a particular Memory Chip Select address space, the Memory Chip Select is not activated. On-chip RAM is not accessible by external devices during Bus Acknowledge cycles.
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RAM Control Registers
RAM Control Register The internal data RAM can be disabled by clearing the RAM_EN bit. The default, upon RESET, is for RAM to be enabled.
Table 113. RAM Control Register (RAM_CTL = 00B4h) Bit Reset CPU Access 7 1 R/W 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R
Note: R/W = Read/Write; R = Read Only.
Bit Position 7 RAM_EN [6:0]
Value 0 1
Description On-chip general-purpose RAM is disabled. On-chip general-purpose RAM is enabled.
0000000 Reserved
RAM Address Upper Byte Register The RAM_ADDR_U register defines the upper byte of the address for the on-chip RAM. If enabled, RAM addresses assume priority over all Chip Selects. The external Chip Select signals are not asserted if the corresponding RAM address is enabled.
Table 114. RAM Address Upper Byte Register (RAM_ADDR_U = 00B5h) Bit Reset CPU Access
Note: R/W = Read/Write.
7 1 R/W
6 1 R/W
5 1 R/W
4 1 R/W
3 1 R/W
2 1 R/W
1 1 R/W
0 1 R/W
Bit Position
Value Description This byte defines the upper byte of the RAM address. On-chip RAM is prioritized over all Memory Chip Selects. If the enabled RAM and Chip Select addresses overlap, the external Chip Select is not asserted.
[7:0] 00h- RAM_ADDR_U FFh
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Flash Memory
Flash Memory Arrangement in the EZ80F92
The EZ80F92 device features 128 KB (131,072 bytes) of nonvolative Flash memory with Read/Write/Erase capability. The main Flash memory array is arranged in 128 pages with 8 rows per page and 128 bytes per row. In addition to main Flash memory, there are two separately-addressable rows which comprise a 256-byte Information Page. The 128 KB of main storage can be protected in eight 16KB blocks. Protecting a 16 KB block prevents Write or Erase operations. The Flash memory arrangement is illustrated in Figure 47.
16 2 KB pages per block F E D C B A 9 8 7 6 5 4 3 2 1 0 8 256-byte rows per page
8 32 KB blocks
7 6
7 6
5 4
5 4
3 2
3 2 256 single-byte columns per row 255 254 1 0
1 0
1 0
Figure 47.EZ80F92 Flash Memory Arrangement
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Flash Memory Arrangement in the eZ80F93
The EZ80F92 features 64 KB (65,536 bytes) of nonvolative Flash memory with Read/ Write/Erase capability. The main Flash memory array is arranged in 64 pages with 8 rows per page and 128 bytes per row. In addition to the main Flash memory there are two separately addressable rows which comprise a 256 byte Information Page. The 64 KB of main storage can be protected in four 16 KB blocks. Protecting a 16 KB block prevents Write or Erase operations. The Flash memory arrangement is illustrated in Figure 48.
16 1-KB pages per block F E 4 16-KB blocks D C B 3 2 A 9 8 7 6 5 4 3 2 1 0 8 128-byte rows per page
7 6 128 single-byte columns per row 127 126 1 0
5 4
1 0
3 2
1 0
Figure 48.eZ80F93 Flash Memory Arrangement
Flash Memory Overview
Flash can be programmed a single byte at a time or in bursts of up to 128 bytes (full row). Write operations may be accomplished using either memory or I/O instructions. Reading Flash memory can be accomplished via internal memory access or through the ZDI and OCI interfaces. The Flash memory controller contains a frequency divider, Flash register interface, address generator, and the Flash control state machine. A simplified block diagram of the Flash controller is illustrated in Figure 49.
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System Clock
Clock Divider 8-bit downcounter
eZ80 Core Interface
ADDR 17 DOUT 8
FADDR FDIN
17 8
FDOUT 8 Flash 256 KB + 512 bytes
FCNTL 9 Flash MAIN_INFO State Machine Flash Control Registers CPUD OUT FLASH_IRQ
8
Figure 49.Flash Memory Block Diagram
Programming Flash Memory
Flash memory is programmed using standard I/O or memory Write operations which the Flash memory controller automatically translates to the detailed timing and protocol required for Flash memory. The more efficient multibyte (row) programming mode is only available via I/O Writes. Caution: To ensure data integrity and device reliability, two main restrictions exist when programming Flash memory: 1. The cumulative programming time subsequent to the most recent Erase cannot exceed 16 ms for any given row. 2. The same byte cannot be programmed more than twice subsequent to the most recent Erase. Single-Byte I/O Write Operations A single-byte I/O Write operation uses I/O registers for setting the column, page, and row address to be programmed. The FLASH_DATA register stores the data to be written. While the CPU executes an output to I/O instruction to load the data into the FLASH_DATA register, the Flash controller asserts the internal WAIT signal to stall the CPU until the Flash Write operation is complete. A single-byte Write takes between 66 s and 85 s to complete. Programming an entire row (128 bytes) using single-byte Writes therefore takes at most 10.8 ms. This measure of time does not include the time required by the CPU to transfer data to the registers, which is a function of the instructions employed and the system clock frequency.
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A typical sequence that performs a single-byte I/O Write is detailed below. Because the Write is self-timed, the sequence can be repeated back-to-back without any necessity for polling or interrupts. 1. Write the FLASH_PAGE, FLASH_ROW, and FLASH_COL registers with the address of the byte to be written. 2. Write the data value to the FLASH_DATA register. Multibyte I/O Write (Row Programming) Multibyte I/O Write operations use the same I/O registers as single-byte Writes, but use an internal address incrementer for subsequent Writes. Multibyte Writes allow programming of a full row and are enabled by setting the ROW_PGM bit of the Flash Program Control Register. For multibyte Writes, the CPU sets the address registers, enables row programming, and then executes a output to I/O instruction with repeat to load the block of data into the FLASH_DATA register. For each individual byte written to the FLASH_DATA register during the block move, the Flash controller asserts the internal WAIT signal to stall the CPU until the current byte has been programmed. During row programming, the Flash controller continuously asserts Flash's high voltage until all bytes are programmed (column address < 127). As a consequence, the row can be programmed faster than if the high voltage is toggled for each byte. The per-byte programming time during row programming is between 41 s and 52 s. As such, programming the 128 bytes of a row in this mode takes at most 6.7 ms, leaving 9.3 ms for the overhead of CPU instructions used to fetch the 128 bytes. A typical sequence that performs a multibyte I/O Write is shown in the following sequence. 1. Check the FLASH_IRQ register to be sure any previous Row Program has completed. 2. Write the FLASH_PAGE, FLASH_ROW, and FLASH_COL registers with the address of the first byte to be written. 3. Set the ROW_PGM bit in the FLASH_PGCTL register to enable row programming mode. 4. Write the next data value to the FLASH_DATA register. 5. If the end of the row has not been reached, return to Step 4. During row programming, software must monitor the row time-out error bit either by enabling this interrupt or through polling. If a row time-out occurs, the Flash controller aborts the row programming operation and software must then assure that no further writes are performed to the row without it first being erased. It is suggested that row programming only be used one time per row and not in combination with single-byte Writes to the same row without first erasing it. Otherwise, the burden is on software to ensure that
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the 16ms maximum cumulative programming time between erasures is not exceeded for a row. Memory Write A single-byte memory Write operation uses the address bus and data bus of the EZ80F92 device for programming a single data byte to Flash. While the CPU executes a LOAD instruction, the Flash controller asserts the internal WAIT signal to stall the CPU until the Write is complete. A single-byte Write takes between 66s and 85s to complete. Programming an entire row using memory Writes therefore takes at most 10.8ms. This time does not include time required by the CPU to transfer data to the registers which is a function of the instructions employed and the system clock frequency. The memory Write function does not support multibyte row programming. Because memory Writes are self-timed, they can be performed back-to-back without any necessity for polling or interrupts.
Erasing Flash Memory
Erasing bytes in Flash memory returns them to a value of FFh. Both the Mass and Page Erase operations are self-timed by the Flash controller, leaving the CPU free to execute other operations in parallel. The DONE status bit in the Flash Interrupt Control Register can be polled by software or used as an interrupt source to signal completion of an Erase operation. If the CPU attempts to access Flash while an Erase is in progress, the Flash controller forces a WAIT state until the Erase operation completes. Mass Erase Performing a Mass Erase operation on Flash memory erases all bits in Flash, including the Information Page. This self-timed operation takes approximately 200 ms to complete. Page Erase The smallest erasable unit in Flash memory is a page. Which of the main Flash memory pages or the single Information Page is to be erased is determined by the setting of the FLASH_PAGE register. This self-timed operation takes approximately 10 ms to complete.
Flash Control Registers
The Flash register interface contains all the registers used in Flash memory. The definitions below describe each register. Flash Key Register Writing the two-byte sequence B6h, 49h in immediate succession to this register unlocks the Flash Divider and Flash Write/Erase Protection registers. If these values are not writ-
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ten by consecutive CPU I/O writes (I/O reads and memory Read/Writes produce no effect), the Flash Divider and Flash Write/Erase Protection registers remain locked to prevent accidental overwrites of these critical Flash control register settings. Writing a value to either the Flash Frequency Divider register or the Flash Write/Erase Protection register automatically relocks both of the registers again.
Table 115. Flash Key Register (FLASH_KEY = 00F5h) Bit Reset CPU Access
Note: W = Write Only.
7 0 W
6 0 W
5 0 W
4 0 W
3 0 W
2 0 W
1 0 W
0 0 W
Bit Position [7:0] FLASH_KEY
Value Description B6h, 49h Sequential Write operations of the values {B6h, 49h} to this register unlock the Flash Frequency Divider and Flash Write/ Erase Protection registers.
Flash Data Register The Flash Data register stores the data values to be programmed to Flash memory via I/O Write operations. This register is used for all I/O Write access to Flash, both individual byte Writes and multibyte row programming. For single-byte I/O Write operations, a single-byte Write to this I/O register programs the data value into the single-byte location pointed to by the page, row, and column registers. For multibyte I/O Write operations, the Flash controller autoincrements the column address for each byte placed into this register. A maximum of 128 bytes of data can be programmed into Flash during a multibyte I/O Write operation. The ROW_PGM bit in the Flash Program Control register must be set to 1 prior to beginning a multibyte I/O Write operation. This register does not return data from Flash memory. If read, this register returns the most recent data value written to the register.
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Table 116. Flash Data Register (FLASH_DATA = 00F6h) Bit Reset CPU Access
Note: R/W = Read/Write.
7 X R/W
6 X R/W
5 X R/W
4 X R/W
3 X R/W
2 X R/W
1 X R/W
0 X R/W
Bit Position [7:0] FLASH_DATA
Value Description 00h- FFh Data value to be written to Flash during an I/O Write operation.
Flash Address Upper Byte Register The FLASH_ADDR_U register defines the upper 7 bits of the address for Flash memory. Changing the value of FLASH_ADDR_U allows the on-chip 128 KB/64 KB Flash memory to be mapped to any location within the 16 MB linear address space of the EZ80F92 device. If the on-chip Flash memory is enabled, Flash address assumes priority over any external Chip Selects. The external Chip Select signals are not asserted if the corresponding Flash address is enabled. The internal Flash memory does not hold priority over internal SRAM.
Table 117. Flash Address Upper Byte Register (FLASH_ADDR_U = 00F7h) Bit Reset CPU Access 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R
Note: R/W = Read/Write; R = Read Only.
Bit Position
Value Description These bits define the upper byte of the Flash address. When on-chip Flash is enabled, the Flash address space begins at address {FLASH_ADDR_U, 0b, 0000h}. On-chip Flash is prioritized over all external Chip Selects. Reserved (enforces alignment on a 128 KB boundary).
[7:1] 00h- FLASH_ADDR_U FEh
0
0
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Flash Control Register The Flash Control register enables or disables memory access to Flash. I/O access to the Flash control registers and I/O programming to Flash memory are still possible while Flash memory space access is disabled. The minimum access time of the internal Flash is 60 ns. The Flash control register must be configured to provide the appropriate number of WAIT states based on the system clock frequency of the EZ80F92 device. Default on RESET is for 4 WAIT states to be inserted for Flash memory access.
Table 118. Flash Control Register (FLASH_CTRL= 00F8h) Bit Reset CPU Access 7 1 R/W 6 0 R/W 5 0 R/W 4 0 R 3 1 R/W 2 0 R 1 0 R 0 0 R
Note: R/W = Read/Write, R = Read Only.
Bit Position [7:5] FLASH_WAIT
Value Description 000 001 010 011 100 101 110 111 0 Wait states are inserted when Flash is active. 1 Wait state is inserted when Flash is active. 2 Wait states are inserted when Flash is active. 3 Wait states are inserted when Flash is active. 4 Wait states are inserted when Flash is active. 5 Wait states are inserted when Flash is active. 6 Wait states are inserted when Flash is active. 7 Wait states are inserted when Flash is active. Reserved Flash Memory Access is disabled. Flash Memory Access is enabled. Reserved
[4] [3] FLASH_EN [2:0]
0 0 1 000
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Flash Frequency Divider Register The 8-bit frequency divider allows programming to Flash over a range of system clock frequencies. Flash can programmed with system clock frequencies ranging from 154 KHz through 50 MHz. The Flash controller requires an input clock with a period that falls within the range of 5.1-6.5 s. The period of the Flash controller clock is set via the Flash Frequency Divider register. Writes to this register are allowed only after it is unlocked via the FLASH_KEY register. The Frequency Divider register value required vs. system clock frequency is detailed in Table 119. System clock frequencies outside of the ranges shown in this table are not supported.
Table 119. Flash Frequency Divider Values System Clock Frequency 154-196 KHz 308-392 KHz 462-588 KHz 616 KHz-50 MHz
Flash Frequency Divider Value 1 2 3 CEILING[System Clock Frequency (MHz) x 5.1 (s)]*
Note: *The CEILING function rounds fractional values up to the next whole number, e.g., CEILING(3.01) is 4.
Table 120. Flash Frequency Divider Register (FLASH_FDIV = 00F9h) Bit Reset CPU Access 7 0 R/W* 6 0 R/W* 5 0 R/W* 4 0 R/W* 3 0 R/W* 2 0 R/W* 1 0 R/W* 0 1 R/W
Note: R/W = Read/Write, R = Read Only. *Key sequence required to enable Writes
Bit Position [7:0] FLASH_FDIV
Value Description 01h- FFh Divider value for generating the required 5.1-6.5 s Flash controller clock period.
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Flash Write/Erase Protection Register The Flash Write/Erase Protection register prevents accidental Write or Erase operations. The protection is limited to a resolution of eight 16 KB blocks. Setting a bit to 1 protects that 16 KB block of Flash memory from accidental writing or erasure. Default on RESET is for all Flash memory blocks to be protected. Note: A protect bit is not available for the Information Page. Mass Erase is prevented if any of the bits in this register are set to 1. Writes to this register are allowed only after it is unlocked via the FLASH_KEY register. Any attempted Writes to this register while locked sets it to FFh, thereby protecting all blocks.
Table 121. Flash Write/Erase Protection Register (FLASH_PROT= 00FAh) Bit Reset CPU Access 7 1 R/W* 6 1 R/W* 5 1 R/W* 4 1 R/W* 3 1 R/W* 2 1 R/W* 1 1 R/W* 0 1 R/W*
Note: R/W = Read/Write if unlocked, R = Read Only if locked. *Key sequence required to unlock.
Bit Position [7]* BLK7_PROT [6]* BLK6_PROT [5]* BLK5_PROT [4]* BLK4_PROT [3] BLK3_PROT [2] BLK2_PROT [1] BLK1_PROT
Value Description 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Disable Write/Erase Protect on block 0x1C000 to 0x1FFFF Enable Write/Erase Protect on block 0x1C000 to 0x1FFFF Disable Write/Erase Protect on block 0x18000 to 0x1BFFF Enable Write/Erase Protect on block 0x18000 to 0x1BFFF Disable Write/Erase Protect on block 0x14000 to 0x17FFF Enable Write/Erase Protect on block 0x14000 to 0x17FFF Disable Write/Erase Protect on block 0x10000 to 0x13FFF Enable Write/Erase Protect on block 0x10000 to 0x13FFF Disable Write/Erase Protect on block 0x0C000 to 0x0FFFF Enable Write/Erase Protect on block 0x0C000 to 0x0FFFF Disable Write/Erase Protect on block 0x08000 to 0x0BFFF Enable Write/Erase Protect on block 0x08000 to 0x0BFFF Disable Write/Erase Protect on block 0x04000 to 0x07FFF Enable Write/Erase Protect on block 0x04000 to 0x07FFF
Note: *Unused in the eZ80F93 device.
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Bit Position [0] BLK0_PROT
Value Description 0 1 Disable Write/Erase Protect on block 0x00000 to 0x03FFF Enable Write/Erase Protect on block 0x00000 to 0x03FFF
Note: *Unused in the eZ80F93 device.
Flash Interrupt Control Register There are two sources of interrupts from the Flash controller. These two sources are:
* *
Page Erase, Mass Erase, or Row Program completed successfully An error condition occurred
Either or both of the two interrupt sources can be enabled by setting the appropriate bits in the Flash Interrupt Control register. The Flash Interrupt Control register contains four status bits to indicate the following error conditions:
*
Row Program Time-out. This bit signals a time-out during Row Programming. If the current Row Program operation does not complete within 2,432 Flash controller clocks (12.4-15.8 ms depending on the Flash controller clock period), the Flash controller terminates the Row Program operation by clearing Bit 2 of the Flash Program Control register and setting the RP_TMO error bit to 1. Write Violation. This bit indicates an attempt to write to a protected block of Flash memory (the Write is not performed). Page Erase Violation. This bit indicates an attempt to erase a protected block of Flash memory (the requested page is not erased). Mass Erase Violation. This bit indicates an attempt to Mass Erase when there are one more protected blocks in Flash memory (the Mass Erase is not performed).
* * *
If the Error Condition Interrupt is enabled, any of the four error conditions result in an interrupt request being sent to the EZ80F92 device's Interrupt Controller. Reading the Flash Interrupt Control register clears all error condition flags and the done flag.
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Table 122. Flash Interrupt Control Register (FLASH_IRQ= 00FBh) Bit Reset CPU Access 7 0 R/W 6 0 R/W 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R
Note: R/W = Read/Write, R = Read Only. Read resets bits [5] and [3:0].
Bit Position [7] DONE_IEN [6] ERR_IEN [5] DONE [4] [3] WR_VIO [2] RP_TMO [1] PG_VIO [0] MASS_VIO
Value Description 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 Flash Erase/Row Program Done Interrupt is disabled Flash Erase/Row Program Done Interrupt is enabled Error Condition Interrupt is disabled Error Condition Interrupt is enabled Erase/Row Program Done Flag is not set Erase/Row Program Done Flag is set Reserved The Write Violation Error Flag is not set. The Write Violation Error Flag is set. The Row Program Time-out Error Flag is not set. The Row Program Time-out Error Flag is set. The Page Erase Violation Error Flag is not set. The Page Erase Violation Error Flag is set. The Mass Erase Violation Error Flag is not set. The Mass Erase Violation Error Flag is set.
Flash Page Select Register The msb of this register is used to select whether all Flash access and Page Erases are directed to the 256-byte Information Page or to the main Flash memory array. When the main array is selected, the lower 7-bits (6 bits in the eZ80F93 device) are used to select one of the 128 pages for Page Erase or I/O Write operations. To perform a Page Erase, the software must set the proper page value prior to setting the Page Erase bit in the Flash control register.
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Table 123. Flash Page Select Register (FLASH_PAGE= 00FCh) Bit Reset CPU Access 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Note: R/W = Read/Write, R = Read Only.
Bit Position [7] INFO_EN
Value Description 0 1 00h- 7Fh Flash accesses main Flash memory. Flash accesses the Information Page. Page Erase and Mass Erase operations affect the Information Page only. Page address of Flash memory to be used during the Page Erase or I/O Write of the main Flash memory. When INFO_EN is set to 1, this field is ignored.
[6:0]* FLASH_PAGE
Note: *Only 6 bits are available in the eZ80F93 device.
Flash Row Select Register The Flash Row Select register is a 3-bit value used to define one of the 8 rows of Flash memory on a single page. This register is used for all I/O Write access to Flash.
Table 124. Flash Row Select Register (FLASH_ROW= 00FDh) Bit Reset CPU Access 7 X R 6 X R 5 X R 4 X R 3 X R 2 0 R/W 1 0 R/W 0 0 R/W
Note: R/W = Read/Write, R = Read Only.
Bit Position [7:3] [2:0] FLASH_ROW
Value Description 00h Reserved.
0h-7h Row address of Flash memory to be used during an I/O Write to Flash memory. When INFO_EN is 1 in the Flash Page Select Register, values for this field are restricted to 0h-1h, which selects between the two rows in the Information Page.
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Flash Column Select Register The column select register is a 7-bit value used to define one of the 128 bytes of Flash memory on a single row. This register is used for all I/O Write access to Flash. This register must be set to the proper column location within a row to program using a single-byte Write operation. In multibyte row programming, this register is used as the start address for the hardware incrementer.
Table 125. Flash Column Select Register (FLASH_COL= 00FEh) Bit Reset CPU Access 7 0 R 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Note: R/W = Read/Write, R = Read Only.
Bit Position [7] [6:0] FLASH_COL
Value Description 0 00h- 7Fh Reserved Column address within a row of Flash memory to be used during an I/O Write of Flash memory.
Flash Program Control Register The Flash program control register is used to perform the functions of Mass Erase, Page Erase, and Row Program. Mass Erase and Page Erase are self-clearing functions. Mass Erase requires approximately 200 ms to erase the full 128 KB/64 KB of main Flash and the 256 byte Information Page. Page Erase requires approximately 10 ms to erase a 1 KB page. Upon completion of either a Mass Erase or Page Erase, the value of the corresponding bit is reset to 0. While Flash is being erased, any Read or Write access of Flash memory force the CPU into a WAIT state until the Erase operation is complete and Flash can be accessed. Reads and Writes to areas other than Flash can proceed as usual while an Erase operation is underway. During row programming, any Reads of Flash memory force a WAIT condition until the row programming operation completes or times out.
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Table 126. Flash Program Control Register (FLASH_PGCTL= 00FFh) Bit Reset CPU Access 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R/W 1 0 R/W 0 0 R/W
Note: R/W = Read/Write, R = Read Only.
Bit Position [7:3] [2] ROW_PGM
Value Description 0000 0 1 Reserved. Row Program Disable or Row Program completed. Row Program Enable. This bit automatically resets to 0 when the row address reaches 128 or when the Row Program operation times out. Page Erase Disable (Page Erase completed) Page Erase Enable. This bit automatically resets to 0 when the Page Erase operation is complete. Mass Erase Disable (Mass Erase completed) Mass Erase Enable. This bit automatically resets to 0 when the Mass Erase operation is complete.
[1] PG_ERASE
0 1
[0] 0 MASS_ERASE 1
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eZ80(R) CPU Instruction Set
Tables 127 through 136 indicate the eZ80(R) CPU instructions available for use with the EZ80F92 device. The instructions are grouped by class. More detailed information is available in the eZ80 CPU User Manual (UM0077).
Table 127. Arithmetic Instructions Mnemonic ADC ADD CP DAA DEC INC MLT NEG SBC SUB Instruction Add with Carry Add without Carry Compare with Accumulator Decimal Adjust Accumulator Decrement Increment Multiply Negate Accumulator Subtract with Carry Subtract without Carry
Table 128. Bit Manipulation Instructions Mnemonic BIT RES SET Instruction Bit Test Reset Bit Set Bit
Table 129. Block Transfer and Compare Instructions Mnemonic CPD (CPDR) CPI (CPIR) LDD (LDDR) LDI (LDIR) Instruction Compare and Decrement (with Repeat) Compare and Increment (with Repeat) Load and Decrement (with Repeat) Load and Increment (with Repeat)
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Table 130. Exchange Instructions Mnemonic EX EXX Instruction Exchange registers Exchange CPU Multibyte register banks
Table 131. Input/Output Instructions Mnemonic IN IN0 IND (INDR) INDRX IND2 (IND2R) INDM (INDMR) INI (INIR) INIRX INI2 (INI2R) INIM (INIMR) OTDM (OTDMR) OTDRX OTIM (OTIMR) OTIRX OUT OUT0 OUTD (OTDR) OUTD2 (OTD2R) OUTI (OTIR) OUTI2 (OTI2R) TSTIO Instruction Input from I/O Input from I/O on Page 0 Input from I/O and Decrement (with Repeat) Input from I/O and Decrement Memory Address with Stationary I/O Address Input from I/O and Decrement (with Repeat) Input from I/O and Decrement (with Repeat) Input from I/O and Increment (with Repeat) Input from I/O and Increment Memory Address with Stationary I/O Address Input from I/O and Increment (with Repeat) Input from I/O and Increment (with Repeat) Output to I/O and Decrement (with Repeat) Output to I/O and Decrement Memory Address with Stationary I/O Address Output to I/O and Increment (with Repeat) Output to I/O and Increment Memory Address with Stationary I/O Address Output to I/O Output to I/O on Page 0 Output to I/O and Decrement (with Repeat) Output to I/O and Decrement (with Repeat) Output to I/O and Increment (with Repeat) Output to I/O and Increment (with Repeat) Test I/O
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Table 132. Load Instructions Mnemonic LD LEA PEA POP PUSH Instruction Load Load Effective Address Push Effective Address Pop Push
Table 133. Logical Instructions Mnemonic AND CPL OR TST XOR Instruction Logical AND Complement Accumulator Logical OR Test Accumulator Logical Exclusive OR
Table 134. Processor Control Instructions Mnemonic CCF DI EI HALT IM NOP RSMIX SCF SLP STMIX Instruction Complement Carry Flag Disable Interrupts Enable Interrupts Halt Interrupt Mode No Operation Reset Mixed-Memory Mode Flag Set Carry Flag Sleep Set Mixed-Memory Mode Flag
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Table 135. Program Control Instructions Mnemonic CALL CALL cc DJNZ JP JP cc JR JR cc RET RET cc RETI RETN RST Instruction Call Subroutine Conditional Call Subroutine Decrement and Jump if Nonzero Jump Conditional Jump Jump Relative Conditional Jump Relative Return Conditional Return Return from Interrupt Return from Nonmaskable interrupt Restart
Table 136. Rotate and Shift Instructions Mnemonic RL RLA RLC RLCA RLD RR RRA RRC RRCA RRD SLA SRA SRL Instruction Rotate Left Rotate Left-Accumulator Rotate Left Circular Rotate Left Circular-Accumulator Rotate Left Decimal Rotate Right Rotate Right-Accumulator Rotate Right Circular Rotate Right Circular-Accumulator Rotate Right Decimal Shift Left Arithmetic Shift Right Arithmetic Shift Right Logical
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Op-Code Map
Tables 137 through 143 indicate the hex values for each of the eZ80(R) CPU instructions.
Table 137. Op Code Map--First Op Code
Legend Upper Op Code Nibble First Operand
0 0 1 2 3 4 5 Upper Nibble (Hex) 6 7 8 9 A B C D NOP DJNZ d JR NZ,d JR NC,d .SIS suffix LD D,B LD H,B LD (HL),B ADD A,B SUB A,B AND A,B OR A,B RET NZ RET NC RET PO RET P
Lower Op Code Nibble 4 A AND A,H
Mnemonic Second Operand
5 DEC B DEC D DEC H DEC (HL) LD B,L LD D,L LD H,L LD (HL),L ADD A,L SUB A,L AND A,L OR A,L PUSH BC PUSH DE PUSH HL PUSH AF Lower Nibble (Hex) 6 7 8 LD B,n LD D,n LD H,n LD (HL),n LD B,(HL) LD D,(HL) LD H,(HL) HALT ADD A,(HL) SUB A,(HL) AND A,(HL) OR A,(HL) ADD A,n SUB A,n AND A,n OR A,n RLCA RLA DAA SCF LD B,A LD D,A LD H,A LD (HL),A ADD A,A SUB A,A AND A,A OR A,A RST 00h RST 10h RST 20h RST 30h EX AF,AF' JR d JR Z,d JR CF,d LD C,B LD E,B LD L,B LD A,B ADC A,B SBC A,B XOR A,B CP A,B RET Z RET CF RET PE RET M 9 ADD HL,BC ADD HL,DE ADD HL,HL ADD HL,SP .LIS suffix LD E,C LD L,C LD A,C ADC A,C SBC A,C XOR A,C CP A,C RET EXX JP (HL) LD SP,HL A LD A,(BC) LD A,(DE) LD HL, (Mmn) LD A, (Mmn) LD C,D LD E,D LD L,D LD A,D ADC A,D SBC A,D XOR A,D CP A,D JP Z, Mmn JP CF, Mmn JP PE, Mmn JP M, Mmn B DEC BC DEC DE DEC HL DEC SP LD C,E .LIL suffix LD L,E LD A,E ADC A,E SBC A,E XOR A,E CP A,E C INC C INC E INC L INC A LD C,H LD E,H LD L,H LD A,H ADC A,H SBC A,H XOR A,H CP A,H CALL Z, Mmn CALL CF, Mmn CALL PE, Mmn CALL M, Mmn D DEC C DEC E DEC L DEC A LD C,L LD E,L LD L,L LD A,L ADC A,L SBC A,L XOR A,L CP A,L CALL Mmn E LD C,n LD E,n LD L,n LD A,n LD C,(HL) LD E,(HL) LD L,(HL) LD A,(HL) ADC A,(HL) SBC A,(HL) XOR A,(HL) CP A,(HL) ADC A,n SBC A,n XOR A,n CP A,n F RRCA RRA CPL CCF LD C,A LD E,A LD L,A LD A,A ADC A,A SBC A,A XOR A,A CP A,A RST 08h RST 18h RST 28h RST 38h
E F
1 2 3 4 LD LD INC INC BC, (BC),A BC B Mmn LD LD INC INC DE, (DE),A DE D Mmn LD LD INC INC HL, (Mmn), HL H Mmn HL LD LD INC INC SP, (Mmn), SP (HL) Mmn A LD LD LD LD B,C B,D B,E B,H LD .SIL LD LD D,C suffix D,E D,H LD LD LD LD H,C H,D H,E H,H LD LD LD LD (HL),C (HL),D (HL),E (HL),H ADD ADD ADD ADD A,C A,D A,E A,H SUB SUB SUB SUB A,C A,D A,E A,H AND AND AND AND A,C A,D A,E A,H OR OR OR OR A,C A,D A,E A,H JP CALL POP JP NZ, NZ, BC Mmn Mmn Mmn JP CALL POP OUT NC, NC, DE (n),A Mmn Mmn JP CALL POP EX PO, PO, HL (SP),HL Mmn Mmn JP CALL POP P, DI P, AF Mmn Mmn
Table 138
IN A,(n) EX DE,HL EI
Table 139 Table 140 Table 141
Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two's-complement displacement.
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Table 138. Op Code Map--Second Op Code after 0CBh
Legend Upper Nibble of Second Op Code First Operand
0 0 1 2 3 4 5 6 7 8 9 A B C D E F BIT 0,B BIT 2,B BIT 4,B BIT 6,B RES 0,B RES 2,B RES 4,B RES 6,B SET 0,B SET 2,B SET 4,B SET 6,B Notes: BIT 0,C BIT 2,C BIT 4,C BIT 6,C RES 0,C RES 2,C RES 4,C RES 6,C SET 0,C SET 2,C SET 4,C SET 6,C BIT 0,D BIT 2,D BIT 4,D BIT 6,D RES 0,D RES 2,D RES 4,D RES 6,D SET 0,D SET 2,D SET 4,D SET 6,D BIT 0,E BIT 2,E BIT 4,E BIT 6,E RES 0,E RES 2,E RES 4,E RES 6,E SET 0,E SET 2,E SET 4,E SET 6,E BIT 0,H BIT 2,H BIT 4,H BIT 6,H RES 0,H RES 2,H RES 4,H RES 6,H SET 0,H SET 2,H SET 4,H SET 6,H BIT 0,L BIT 2,L BIT 4,L BIT 6,L RES 0,L RES 2,L RES 4,L RES 6,L SET 0,L SET 2,L SET 4,L SET 6,L BIT 0,(HL) BIT 2,(HL) BIT 4,(HL) BIT 6,(HL) RES 0,(HL) RES 2,(HL) RES 4,(HL) RES 6,(HL) SET 0,(HL) SET 2,(HL) SET 4,(HL) SET 6,(HL) BIT 0,A BIT 2,A BIT 4,A BIT 6,A RES 0,A RES 2,A RES 4,A RES 6,A SET 0,A SET 2,A SET 4,A SET 6,A RLC B RL B SLA B 1 RLC C RL C SLA C 2 RLC D RL D SLA D
Lower Nibble of 2nd Op Code 4 RES A 4,H
Mnemonic Second Operand
Lower Nibble (Hex) 3 RLC E RL E SLA E 4 RLC H RL H SLA H 5 RLC L RL L SLA L 6 RLC (HL) RL (HL) SLA (HL) 7 RLC A RL A SLA A 8 RRC B RR B SRA B SRL B BIT 1,B BIT 3,B BIT 5,B BIT 7,B RES 1,B RES 3,B RES 5,B RES 7,B SET 1,B SET 3,B SET 5,B SET 7,B 9 RRC C RR C SRA C SRL C BIT 1,C BIT 3,C BIT 5,C BIT 7,C RES 1,C RES 3,C RES 5,C RES 7,C SET 1,C SET 3,C SET 5,C SET 7,C A RRC D RR D SRA D SRL D BIT 1,D BIT 3,D BIT 5,D BIT 7,D RES 1,D RES 3,D RES 5,D RES 7,D SET 1,D SET 3,D SET 5,D SET 7,D B RRC E RR E SRA E SRL E BIT 1,E BIT 3,E BIT 5,E BIT 7,E RES 1,E RES 3,E RES 5,E RES 7,E SET 1,E SET 3,E SET 5,E SET 7,E C RRC H RR H SRA H SRL H BIT 1,H BIT 3,H BIT 5,H BIT 7,H RES 1,H RES 3,H RES 5,H RES 7,H SET 1,H SET 3,H SET 5,H SET 7,H D RRC L RR L SRA L SRL L BIT 1,L BIT 3,L BIT 5,L BIT 7,L RES 1,L RES 3,L RES 5,L RES 7,L SET 1,L SET 3,L SET 5,L SET 7,L E RRC (HL) RR (HL) SRA (HL) SRL (HL) BIT 1,(HL) BIT 3,(HL) BIT 5,(HL) BIT 7,(HL) RES 1,(HL) RES 3,(HL) RES 5,(HL) RES 7,(HL) SET 1,(HL) SET 3,(HL) SET 5,(HL) SET 7,(HL) F RRC A RR A SRA A SRL A BIT 1,A BIT 3,A BIT 5,A BIT 7,A RES 1,A RES 3,A RES 5,A RES 7,A SET 1,A SET 3,A SET 5,A SET 7,A
Upper Nibble (Hex)
n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two's-complement displacement.
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Table 139. Op Code Map--Second Op Code After 0DDh
Legend Upper Nibble of Second Op Code First Operand
0 0 1 2
Lower Nibble of 2nd Op Code 9 F LD SP,IX
Mnemonic Second Operand
3 4 5 6 Lower Nibble (Hex) 7 8 LD BC, (IX+d) LD DE, (IX+d) 9 ADD IX,BC ADD IX,DE ADD IX,IX ADD IX,SP LD C,IXH LD E,IXH LD IXH,A LD (IX+d),A ADD A, (IX+d) SUB A, (IX+d) AND A, (IX+d) OR A, (IX+d) Table 142 LD IXL,B LD IXL,C LD IXL,D LD IXL,E LD C,IXL LD E,IXL LD IX, (Mmn) DEC IX INC IXL DEC IXL A B C D F LD (IX+d), BC LD (IX+d), DE LD LD (IX+d), IXL,n HL LD LD (IX+d), (IX+d), IY IX LD C, (IX+d) LD E, (IX+d) LD IXL,A E
1 LD IX, Mmn LD IY, (IX+d) LD (Mmn), IX INC IX INC IXH INC (IX+d) LD B,IXH LD D,IXH LD IXH,B LD IXH,C LD IXH,D DEC IXH DEC (IX+d) LD B,IXL LD D,IXL LD IXH,n LD (IX +d),n LD B, (IX+d) LD D, (IX+d)
2
LD HL, (IX+d) LD IX, (IX+d)
3 4 5 Upper Nibble (Hex) 6 7 8 9 A B C D E F Notes:
LD LD LD LD H, IXH,E IXH,IXH IXH,IXL (IX+d)
LD LD LD L, IXL,IXH IXL,IXL (IX+d) LD LD A, LD A,IXL A,IXH (IX+d) ADC A,IXH SBC A,IXH XOR A,IXH CP A,IXH ADC A,IXL SBC A,IXL XOR A,IXL CP A,IXL ADC A, (IX+d) SBC A, (IX+d) XOR A, (IX+d) CP A, (IX+d)
LD LD LD LD LD LD (IX+d),B (IX+d),C (IX+d),D (IX+d),E (IX+d),H (IX+d),L ADD A,IXH SUB A,IXH AND A,IXH OR A,IXH ADD A,IXL SUB A,IXL AND A,IXL OR A,IXL
POP IX
EX (SP),IX
PUSH IX
JP (IX) LD SP,IX
n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two's-complement displacement.
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Table 140. Op Code Map--Second Op Code After 0EDh
Legend Upper Nibble of Second Op Code First Operand
0 IN0 B,(n) IN0 D,(n) IN0 H,(n)
Lower Nibble of 2nd Op Code 2 SBC 4 HL,BC
Mnemonic Second Operand
Lower Nibble (Hex) 4 TST A,B TST A,D TST A,H 5 6 7 LD BC, (HL) LD DE, (HL) LD HL, (HL) LD IX, (HL) IM 0 LD I,A LD A,I RRD 8 IN0 C,(n) IN0 E,(n) IN0 L,(n) IN0 A,(n) IN C,(C) IN E,(C) IN L,(C) IN A,(C) 9 OUT0 (n),C OUT0 (n),E OUT0 (n),L OUT0 (n),A OUT (C),C OUT (C),E OUT (C),L OUT (C),A ADC HL,BC ADC HL,DE ADC HL,HL ADC HL,SP INDM LD BC, (Mmn) LD DE, (Mmn) LD HL, (Mmn) LD SP, (Mmn) OTDM A B C TST A,C TST A,E TST A,L TST A,A MLT BC MLT DE MLT HL MLT SP IND2 RETI D E F LD (HL), BC LD(HL), DE LD (HL), HL LD LD (HL), (HL),IY IX LD R,A IM 2 LD A,R
0 1 2 3 4
1 2 3 OUT0 LEA BC, LEA BC, (n),B IX+d IY+d OUT0 LEA DE, LEA DE, (n),D IX+d IY+d OUT0 LEA HL LEA HL (n),H ,IX+d ,IY+d LD IY, (HL)
5
Upper Nibble (Hex)
6
7 8 9 A B C D E F
LEA IX LEA IY TST ,IX+d ,IY+d A,(HL) LD IN OUT SBC (Mmn), NEG RETN B,(BC) (BC),B HL,BC BC LD IN OUT SBC LEA IX, LEA IY, (Mmn), D,(BC) (BC),D HL,DE IY+d IX+d DE LD IBN OUT SBC TST PEA (Mmn), H,(C) (BC),H HL,HL A,n IX+d HL LD SBC TSTIO (Mmn), HL,SP n SP INIM OTIM INI2 INI2R OUTI2 OTI2R
IM 1 PEA IY+d SLP
LD LD A,MB RLD MB,A STMIX RSMIX
INIMR OTIMR LDI LDIR CPI CPIR INI INIR INIRX OUTI OTIR OTIRX
INDMR OTDMR IND2R LDD LDDR CPD CPDR IND INDR OUTD OUTD2 OTDR OTD2R
INDRX OTDRX
Notes:
n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two's-complement displacement.
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Table 141. Op Code Map--Second Op Code After 0FDh
Legend Upper Nibble of Second Op Code First Operand
0 0 1 2 3 4 5 Upper Nibble (Hex) 6 7 8 9 A B C D E F Notes: POP IY EX (SP),IY PUSH IY JP (IY) LD SP,IY n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two's-complement displacement. LD IYH,B LD (IY +d),B LD IYH,C LD (IY +d),C LD IYH,D LD (IY +d),D LD LD (Mmn),I IY,Mmn Y LD IX, (IY+d) INC IY INC IYH INC (IY+d) DEC IYH DEC (IY+d) LD IYH,n LD (IY +d),n 1 2
Lower Nibble of 2nd Op Code 9 LD F SP,IY
Mnemonic Second Operand
3 4 5 6 Lower Nibble (Hex) 7 8 9 LD BC, ADD (IY+d) IY,BC LD DE, (IY+d) LD HL, (IY+d) LD IY, (IY+d) ADD IY,DE ADD IY,IY ADD IY,SP LD C,IYH LD C,IYL LD IY, (Mmn) DEC IY INC IYL DEC IYL LD IYL,n LD (IY +d),IX LD C, (IY+d) A B C D E F LD (IY +d),BC LD (IY +d),DE LD (IY +d),HL LD (IY +d),IY
LD LD B, LD B,IYL B,IYH (IY+d) LD D,IYH LD D,IYL LD D, (IY+d) LD LD LD IYL,B IYH,A IYL,C LD (IY +d),A ADD A, (IY+d) SUB A, (IY+d) AND A, (IY+d) OR A, (IY+d)
LD LD E, LD E,IYL E,IYH (IY+d) LD LD LD LD L, LD IYL,E LD IYL,A IYL,D IYL,IYH IYL,IYL (IY+d) LD LD A, LD A,IYL A,IYH (IY+d) ADC A,IYH SBC A,IYH XOR A,IYH CP A,IYH ADC A,IYL SBC A,IYL XOR A,IYL CP A,IYL ADC A, (IY+d) SBC A, (IY+d) XOR A, (IY+d) CP A, (IY+d)
LD LD LD LD H, IYH,E IYH,IYH IYH,IYL (IY+d) LD (IY +d),E LD (IY +d),H ADD A,IYH SUB A,IYH AND A,IYH OR A,IYH LD (IY +d),L ADD A,IYL SUB A,IYL AND A,IYL OR A,IYL
Table 143
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Table 142. Op Code Map--Fourth Byte After 0DDh, 0CBh, and dd
Legend Upper Nibble of Fourth Byte First Operand
0 0 1 2 3 4 5 Upper Nibble (Hex) 6 7 8 9 A B C D E F Notes: d = 8-bit two's-complement displacement. BIT 0, (IX+d) BIT 2, (IX+d) BIT 4, (IX+d) BIT 6, (IX+d) RES 0, (IX+d) RES 2, (IX+d) RES 4, (IX+d) RES 6, (IX+d) SET 0, (IX+d) SET 2, (IX+d) SET 4, (IX+d) SET 6, (IX+d) 1 2
Lower Nibble of 4th Byte 6 BIT 4 0,(IX+d)
Mnemonic Second Operand
3 4 5 Lower Nibble (Hex) 6 7 8 RLC (IX+d) RL (IX+d) SLA (IX+d) 9 A B C D E RRC (IX+d) RR (IX+d) SRA (IX+d) SRL (IX+d) BIT 1, (IX+d) BIT 3, (IX+d) BIT 5, (IX+d) BIT 7, (IX+d) RES 1, (IX+d) RES 3, (IX+d) RES 5, (IX+d) RES 7, (IX+d) SET 1, (IX+d) SET 3, (IX+d) SET 5, (IX+d) SET 7, (IX+d) F
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Table 143. Op Code Map--Fourth Byte After 0FDh, 0CBh, and dd*
Legend Upper Nibble of Fourth Byte Lower Nibble of 4th Byte
6 BIT Mnemonic 4 0,(IY+d) First Operand Second Operand
0 0 1 2 3 4 5 Upper Nibble (Hex) 6 7 8 9 A B C D E F Notes: d = 8-bit two's-complement displacement. BIT 0, (IY+d) BIT 2, (IY+d) BIT 4, (IY+d) BIT 6, (IY+d) RES 0, (IY+d) RES 2, (IY+d) RES 4, (IY+d) RES 6, (IY+d) SET 0, (IY+d) SET 2, (IY+d) SET 4, (IY+d) SET 6, (IY+d) 1 2 3 4 5 Lower Nibble (Hex) 6 7 8 RLC (IY+d) RL (IY+d) SLA (IY+d) 9 A B C D E RRC (IY+d) RR (IY+d) SRA (IY+d) SRL (IY+d) BIT 1, (IY+d) BIT 3, (IY+d) BIT 5, (IY+d) BIT 7, (IY+d) RES 1, (IY+d) RES 3, (IY+d) RES 5, (IY+d) RES 7, (IY+d) SET 1, (IY+d) SET 3, (IY+d) SET 5, (IY+d) SET 7, (IY+d) F
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On-Chip Oscillators
The EZ80F92 device features two on-chip oscillators for use with an external crystal. The primary oscillator generates the system clock for the internal CPU and the majority of the on-chip peripherals. Alternatively, the XIN input pin can also accept a CMOS-level clock input signal. If an external clock generator is used, the XOUT pin should be left unconnected. The secondary oscillator can drive a 32 KHz crystal to generate the time-base for the Real-Time Clock.
20 MHz Primary Crystal Oscillator Operation
Figure 50 illustrates a recommended configuration for connection with an external 20MHz, fundamental-mode, parallel-resonant crystal. Recommended crystal specifications are provided in Table 144. Resistor R1 limits total power dissipation by the crystal. Printed circuit board layout should add no more than 4pF of stray capacitance to either the XIN or XOUT pins. If oscillation does not occur, reduce the values of capacitors C1 and C2 to decrease loading.
On-Chip Oscillator
XIN
XOUT
20 MHz Crystal (Fundamental Mode)
R1 = 220
C2 = 22 pF
R2 = 100 K
C2 = 22 pF
Figure 50.Recommended Crystal Oscillator Configuration (20MHz operation)
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Table 144. Recommended Crystal Oscillator Specifications (20 MHz Operation) Parameter Frequency Resonance Mode Series Resistance (RS) Load Capacitance (CL) Shunt Capacitance (C0) Drive Level Value 20 Parallel Fundamental 25 20 7 1 pF pF m Maximum Maximum Maximum Maximum Units MHz Comments
32 KHz Real-Time Clock Crystal Oscillator Operation
Figure 51 illustrates a recommended configuration for connecting the Real-Time Clock oscillator with an external 32 KHz, fundamental-mode, parallel-resonant crystal. The recommended crystal specifications are provided in Table 145. A printed circuit board layout should add no more than 4 pF of stray capacitance to either the RTC_XIN or RTC_XOUT pins. If oscillation does not occur, reduce the values of capacitors C1 and C2 to decrease loading. An on-chip MOS resistor sets the crystal drive current limit. This configuration does not require an external bias resistor across the crystal. An on-chip MOS resistor provides the biasing.
On-Chip Oscillator
RTC_XIN
RTC_XOUT
32 MHz Crystal (Fundamental Mode)
R1 = 220
C2 = 18 pF
C2 = 18 pF
Figure 51.Recommended Crystal Oscillator Configuration (32KHz operation)
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Table 145. Recommended Crystal Oscillator Specifications (32 KHz Operation) Parameter Frequency Resonance Mode Series Resistance (RS) Load Capacitance (CL) Shunt Capacitance (C0) Drive Level Value 32 Parallel Fundamental 40 12.5 3 1 K pF pF Maximum Maximum Maximum Maximum Units KHz Comments 32768 Hz
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Electrical Characteristics
Absolute Maximum Ratings
Stresses greater than those listed in Table 146 may cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, unused inputs should be tied to one of the supply voltages (VDD or VSS).
Table 146. Absolute Maximum Ratings Parameter Ambient temperature under bias (C) Storage temperature (C) Voltage on any pin with respect to VSS Voltage on VDD pin with respect to VSS Total power dissipation Maximum current out of VSS Maximum current into VDD Maximum current on input and/or inactive output pin Maximum output current from active output pin
Notes: 1. Operating temperature is specified in DC Characteristics. 2. This voltage applies to all pins except where noted otherwise.
Min -40 -65 -0.3 -0.3
Max +105 +150 +5.5 +3.6 520 145 145
Units C C V V mW mA mA A mA
Notes 1
2
-25 -8
+25 +8
DC Characteristics
Table 147 lists the DC characteristics of the EZ80F92 device. Note: All data is preliminary and subject to change following completion of production characterization.
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Table 147. DC Characteristics TA = 0C to 70C Symbol VDD VIL VIH VOL VOH IIL ITL IPU Parameter Supply Voltage Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Input Leakage Current Tristate Leakage Current Internal Pull-Up Current Power Dissipation (normal operation) 2.4 -10 -10 +10 +10 100 Typical 33 Typical Min 3.0 -0.3 0.7 x VDD Max 3.6 0.8 5.5 0.4 2.4 -20 -20 +20 +20 100 Typical 33 Typical TA = 0C to 105C Min 3.0 -0.3 0.7 x VDD Max 3.6 0.8 5.5 0.4 Units Conditions V V V V V A A A mA VDD = 3.0 V; IOL = 1 mA VDD = 3.0 V; IOH = -1 mA VDD = 3.6V; VIN = VDD or VSS1 VDD = 3.6 V VDD = 3.6 V; 25C F = 20 MHz; VDD = 3.3V; 7 Wait States; 25C F = 20 MHz; VDD = 3.3V; 25C VDD = 3.3V; 25C
Power Dissipation (HALT mode) Power Dissipation (SLEEP mode) RTC Supply Voltage RTC Supply Current IRTC 3.0 2.5
21 Typical 375 Typical 3.6 10 Typical 3.0 2.5
21 Typical 600 Typical 3.6 10 Typical
mA
A V A
IDD RTC_VDD
Supply current into RTC_VDD; SLEEP mode2.
Notes: 1. This condition excludes all pins with on-chip pull-ups when driven Low. 2. RTC current increases when the EZ80F92 device is not in SLEEP mode as the RTC_VDD pin supplies power to system clock buffers within the Real-Time Clock circuit.
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POR and VBO Electrical Characteristics
Table 147 lists the Power-On Reset and Voltage Brown-Out characteristics of the EZ80F92 device.
Table 148. POR and VBO Electrical Characteristics TA = 0C to +105C Symbol VVBO VPOR VHYST TANA TVBO_MIN VCCRAMP Parameter VBO Voltage Threshold POR Voltage Threshold POR/VBO Hysteresis Min 2.40 2.45 50 Typ 2.55 2.65 100 Max 2.85 2.90 150 100 10 0.1 100 Unit V V mV s s V/ms Conditions VCC = VVBO VCC = VPOR.
POR/VBO analog RESET duration 40 VBO pulse reject period VCC ramp rate requirements to guarantee proper RESET occurs
Typical Current Consumption Under Various Operating Conditions
In the following pages, Figure 52 illustrates the typical current consumption of the EZ80F92 device versus the number of WAIT states while operating 25 C, 3.3V, and with either a 1 MHz, 10 MHz, 15 MHz or 20 MHz system clock. Figure 53 illustrates the typical current consumption of the EZ80F92 device versus the system clock frequency while operating 25 C, 3.3V, and using 0, 2, or 7 WAIT states. Figure 54 illustrates the typical current consumption of the EZ80F92 device versus temperature while operating at 3.3V, 7 WAIT states, and with either a 1 MHz, 10 MHz, 15 MHz or 20 MHz system clock. Figure 55 illustrates the typical current consumption of the EZ80F92 device versus system clock frequency while operating in HALT mode. Figure 56 illustrates the typical current consumption of the EZ80F92 device versus temperature while operating in SLEEP mode.
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ICC vs. WAIT States (Typical @ 3.3V, 25C)
60.00
50.00
40.00
Current (mA)
30.00
5 MHz 10 MHz 15 MHz 20 MHz
20.00
10.00
0.00 0 1 2 3 WAIT States 4 5 6 7
Figure 52.ICC Versus WAIT States as a Function of Frequency
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ICC vs. Frequency (Typical @3.3V, 25C)
60.00
50.00
40.00
Current (mA)
30.00
0 WAIT 2 WAIT 7 WAIT
20.00
10.00
0.00 5 10 Frequency (MHz) 15 20
Figure 53.ICC Versus Frequency as a Function of WAIT States
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ICC versus Temp with 7 WAIT States (Typical @ 3.3V)
40.00
35.00
30.00
25.00
Current (mA)
20.00
5 MHz 10 MHz 15 MHz 20 MHz
15.00
10.00
5.00
0.00 0 20 40 60 Temperature (C) 80 100
Figure 54.ICC Versus Temperature as a Function of Frequency
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ICC vs. Frequency in HALT mode (Typical @ 3.3V)
25
20
15
Current (mA)
10
5
0 0 5 10 Frequency (MHz) 15 20
Figure 55.ICC Versus Frequency in HALT Mode
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ICC vs. Temperature in SLEEP mode (Typical @ 3.3V, RTC operating at 32KHz)
450
400
350
300
Current (uA)
250
200
150
100
50
0 0 20 40 60 Temperature (C) 80 100
Figure 56.ICC Versus Temperature in SLEEP Mode
AC Characteristics
The section provides information about the AC characteristics and timing of the EZ80F92 device. All AC timing information assumes a standard load of 50 pF on all outputs. See Table 149. Note: All data is preliminary and subject to change following completion of production characterization.
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Table 149. AC Characteristics TA = 0C to 70C Symbol Parameter TXIN TXINH TXINL TXINR TXINF System Clock Cycle Time System Clock High Time System Clock Low Time System Clock Rise Time System Clock Fall Time Min 50 20 20 3 3 Max TA = 0C to 105C Min 50 20 20 3 3 Max Units ns ns ns ns ns Conditions VDD = 3.0-3.6V VDD = 3.0-3.6V; TCLK = 50ns VDD = 3.0-3.6V; TCLK = 50ns VDD = 3.0-3.6V; TCLK = 50ns VDD = 3.0-3.6V; TCLK = 50ns
External Memory Read Timing
Figure 57 and Table 150 diagram the timing for external reads.
TCLK X IN T1 ADDR[23:0] T3 DATA[7:0] (input) T5 CSx T7 MREQ T9 RD T10 T8 T6 T4 T2
Figure 57.External Memory Read Timing
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Table 150. External Read Timing Delay (ns) Parameter T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Abbreviation Clock Rise to ADDR Valid Delay Clock Rise to ADDR Hold Time Input DATA Valid to Clock Rise Setup Time Clock Rise to DATA Hold Time Clock Rise to CSx Assertion Delay Clock Rise to CSx Deassertion Delay Clock Rise to MREQ Assertion Delay Clock Rise to MREQ Deassertion Delay Clock Rise to RD Assertion Delay Clock Rise to RD Deassertion Delay Min -- 2.0 1.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 Max 13 -- -- -- 19.0 18.0 16.0 16.0 16.0 16.0
External Memory Write Timing
Figure 58 and Table 151 diagram the timing for external writes.
TCLK X IN T1 ADDR[23:0] T3 DATA[7:0] (output) T5 CSx T7 MREQ T9 WR T10 T8 T6 T4 T2
Figure 58.External Memory Write Timing
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Table 151. External Write Timing Delay (ns) Parameter T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Abbreviation Clock Rise to ADDR Valid Delay Clock Rise to ADDR Hold Time Clock Fall to Output DATA Valid Delay Clock Rise to DATA Hold Time Clock Rise to CSx Assertion Delay Clock Rise to CSx Deassertion Delay Clock Rise to MREQ Assertion Delay Clock Rise to MREQ Deassertion Delay Clock Fall to WR Assertion Delay Clock Rise to WR Deassertion Delay* WR Deassertion to ADDR Hold Time WR Deassertion to DATA Hold Time WR Deassertion to CSx Hold Time WR Deassertion to MREQ Hold Time Min -- 2.0 -- 2.0 2.0 2.0 2.0 2.0 1.8 1.6 0.25 0.25 0.25 0.25 Max 13 -- 11 -- 19.0 18.0 16.0 16.0 6.5 6.5 -- -- -- --
Note: *At the conclusion of a Write cycle, deassertion of WR always occurs before any change to ADDR, DATA, CSx, or MREQ.
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External I/O Read Timing
Figure 59 and Table 152 diagram the timing for external I/O Reads. Clock rise/fall to signal transition timing is independent of the particular bus mode employed (eZ80, Z80, IntelTM, or Motorola).
TCLK X IN T1 ADDR[23:0] T3 DATA[7:0] (input) T5 CSx T7 IORQ T9 RD T10 T8 T6 T4 T2
Figure 59.External I/O Read Timing
Table 152. External I/O Read Timing Delay (ns) Parameter T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Abbreviation Clock Rise to ADDR Valid Delay Clock Rise to ADDR Hold Time Input DATA Valid to Clock Rise Setup Time Clock Rise to DATA Hold Time Clock Rise to CSx Assertion Delay Clock Rise to CSx Deassertion Delay Clock Rise to IORQ Assertion Delay Clock Rise to IORQ Deassertion Delay Clock Rise to RD Assertion Delay Clock Rise to RD Deassertion Delay Min -- 2.0 1.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 Max 13 -- -- -- 19.0 18.0 16.0 16.0 16.0 16.0
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External I/O Write Timing
Figure 60 and Table 153 diagram the timing for external I/O writes. Clock rise/fall to signal transition timing is independent of the particular bus mode employed (eZ80, Z80, IntelTM, or Motorola).
TCLK X IN T1 ADDR[23:0] T3 DATA[7:0] (output) T5 CSx T7 IORQ T9 WR T10 T8 T6 T4 T2
Figure 60.External I/O Write Timing Table 153. External I/O Write Timing Delay (ns) Parameter T1 T2 T3 T4 T5 T6 T7 T8 Abbreviation Clock Rise to ADDR Valid Delay Clock Rise to ADDR Hold Time Clock Fall to Output DATA Valid Delay Clock Rise to DATA Hold Time Clock Rise to CSx Assertion Delay Clock Rise to CSx Deassertion Delay Clock Rise to IORQ Assertion Delay Clock Rise to IORQ Deassertion Delay Min -- 2.0 -- 2.0 2.0 2.0 2.0 2.0 Max 13 -- 11 -- 19.0 18.0 16.0 16.0
Note: *At the conclusion of a Write cycle, deassertion of WR always occurs before any change to ADDR, DATA, CSx, or IORQ.
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Table 153. External I/O Write Timing (Continued) Delay (ns) Parameter T9 T10 Abbreviation Clock Fall to WR Assertion Delay Clock Rise to WR Deassertion Delay* WR Deassertion to ADDR Hold Time WR Deassertion to DATA Hold Time WR Deassertion to CSx Hold Time WR Deassertion to IORQ Hold Time Min 1.8 1.6 0.25 0.25 0.25 0.25 Max 6.5 6.5 -- -- -- --
Note: *At the conclusion of a Write cycle, deassertion of WR always occurs before any change to ADDR, DATA, CSx, or IORQ.
Wait State Timing for Read Operations
Figure 61 illustrates the extension of the memory access signals using a single WAIT state for a Read operation. This WAIT state is generated by setting CS_WAIT to 001h in the Chip Select Control Register.
TCLK
X IN
TWAIT
ADDR[23:0]
DATA[7:0] (output)
CSx
MREQ
RD
INSTRD
Figure 61.Wait State Timing for Read Operations
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Wait State Timing for Write Operations
Figure 62 illustrates the extension of the memory access signals using a single WAIT state for a Write operation. This WAIT state is generated by setting CS_WAIT to 001h in the Chip Select Control Register.
TCLK
X IN
TWAIT
ADDR[23:0]
DATA[7:0] (output)
CSx
MREQ
WR
Figure 62.Wait State Timing for Write Operations
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General Purpose I/O Port Input Sample Timing
Figure 63 illustrates timing of the GPIO input sampling. The input value on a GPIO port pin is sampled on the rising edge of the system clock. The port value is then available to the CPU on the second rising clock edge following the change of the port value.
TCLK
System Clock Port Value Changes to 0 GPIO Pin Input Value
GPIO Input Data Latch
0 Latched Into GPIO Data Register GPIO Data Register Value 0 Read by eZ80
GPIO Data READ on Data Bus
Figure 63.Port Input Sample Timing
Table 154. GPIO Port Output Timing Delay (ns) Parameter T1 Abbreviation Clock Rise to Port Output Delay Min 2.0 Max 15.0
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External Bus Acknowledge Timing
Table 155 provides information about the bus acknowledge timing. Once the external bus master detects BUSACK asserted and drives IORQN, MREQN, A[23:0] there is an asynchronous prop delay to the CS[3:0] outputs being valid.
Table 155. Bus Acknowledge Timing Delay (ns) Parameter T1 T2 T3 Abbreviation Clock Rise to BUSACK Assertion Delay Clock Rise to BUSACK Deassertion Delay IORQN, MREQN, A[23:0] input to CS[3:0] output prop delay Min 2.0 2.0 -- Max 14.0 14.0 10.0
External System Clock Driver (PHI) Timing
Table 156 provides timing information for the PHI pin. The PHI pin allows external peripherals to synchronize with the internal system clock driver on the EZ80F92 device.
Table 156. PHI System Clock Timing Delay (ns) Parameter T1 T2 Abbreviation Clock (XIN) Rise to PHI Rise Clock (XIN) Fall to PHI Fall Min -- -- Max 6.0 6.0
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ZiLOG Debug Interface Timing
Figure 64 and Table 157 provide timing information for TCK, TDI, TDO, TMS pins.
TCK T1 TDI TMS
T2
T3 TDO
Figure 64.ZDI Timing
Table 157. ZDI Timing Specifications Delay (ns) Parameter TTCK T1 T2 T3 Abbreviation TCK Period TDI/TMS setup to TCK Rise TDI/TMS hold after TCK Rise Fall TCK Rise to TDO change Min 2 x TXIN 4 4 10 Max
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Packaging
Figure 65 illustrates the 100-pin low-profile quad flat package (LQFP) for the EZ80F92 device.
Figure 65.100-Lead Plastic Low-Profile Quad Flat Package (LQFP)
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Ordering Information
Table 158 provides a part name, a product specification index code, and a brief description of each part.
Table 158. Ordering Information Part Name EZ80F92 PSI EZ80F92AZ020SC, EZ80F92AZ020SG EZ80F92AZ020EC, EZ80F92AZ020EG eZ80F93 eZ80F93AZ020SC, eZ80F93AZ020SG eZ80F93AZ020EC, eZ80F93AZ020EG Description 100-pin LQFP, 128 KB Flash memory, 8 KB SRAM, 20 MHz, Standard Temperature. 100-pin LQFP, 128 KB Flash memory, 8 KB SRAM, 20 MHz, Extended Temperature. 100-pin LQFP, 64 KB Flash memory, 4 KB SRAM, 20 MHz, Standard Temperature. 100-pin LQFP, 64 KB Flash memory, 4 KB SRAM, 20 MHz, Extended Temperature.
Navigate your browser to ZiLOG's website to order the EZ80F92 or the eZ80F93. Or, contact your local ZiLOG Sales Office to order these devices. ZiLOG provides additional assistance on its Customer Service page, and is also here to help with technical support issues. For ZILOG's valuable software development tools and downloadable software, visit the ZiLOG website.
Part Number Description
ZiLOG part numbers consist of a number of components, as indicated in the following examples:
ZiLOG Base Products eZ80 F92 AZ 020 S or E C or G ZiLOG eZ80(R) CPU Product Number Package Speed Temperature Environmental Flow
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Package Speed Standard Temperature Extended Temperature Environmental Flow
AZ = LQFP (also called the VQFP) 020 = 20 MHz S = 0C to +70C E = -40C to +105C C = Plastic Standard; G = Lead-Free
Example. Part number EZ80F92AZ020SC is an eZ80Acclaim!TM product in an LQFP
package, operating with a 20 MHz external clock frequency over a 0C to +70C temperature range and built using the Plastic Standard environmental flow.
Precharacterization Product
The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows about this product at this time, but additional features or nonconformance with some aspects of the document might be found, either by ZiLOG or its customers in the course of further application and characterization work. In addition, ZiLOG cautions that delivery might be uncertain at times, due to start-up yield issues. ZiLOG, Inc. 532 Race Street San Jose, CA 95126 Telephone (408) 558-8500 FAX 408 558-8300 Internet: www.zilog.com
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Document Information
Document Number Description
The Document Control Number that appears in the footer on each page of this document contains unique identifying attributes, as indicated in the following table:
PS 0153 08 0404 Product Specification Unique Document Number Revision Number Month and Year Published
Change Log
Rev 01 02 03 04 05 06 07 08 Date 06/02 01/03 01/03 02/03 08/03 08/03 02/04 04/04 Purpose Original issue Technical Updates Technical Updates Modified hyperlinks/refs. Modified extended temp. Minor revision By J. Eversmann/R. Beebe J. Eversmann M. Richmond, R. Beebe A. Abuhakmeh, A. Koontz R. Xue, A. Shaw R. Beebe
Revised BRG in UART section C. Bender Added cautions for SLP/HLT C. Bender
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Index
Numerics
100-pin LQFP package 4, 20 16-bit clock divisor value 110, 135 16-bit divisor count 110, 135 20 MHz Primary Crystal Oscillator Operation 218 32 KHz Real-Time Clock Crystal Oscillator Operation 219 Bus Enable bit 154, 156 Bus Mode Controller 54 bus mode state 54-55, 58, 62, 66, 72 Bus Modes 54, 67, 71 Bus Request 11, 22, 53, 168, 178, 184 During ZDI Debug Mode 168 BUSACK--see Bus Acknowledge BUSREQ--see Bus Request Byte Format 142
A
AAK--see I2C Acknowledge bit Absolute Maximum Ratings 221 AC Characteristics 228 ACK--see Acknowledge Acknowledge 142, 146-150, 152, 157 address bus 5-9, 47, 51, 53-58, 61, 64-65, 68-69, 90, 168, 178, 184 address bus, 24-bit 24 Addressing 152 ADL Memory mode 180, 184 alarm condition 89, 102, 103 Arbitration 144 Architectural Overview 1 asynchronous serial data 12, 15
C
Change Log 242 Characteristics, electrical Absolute maximum ratings 221 Chip Select 0 9 Chip Select 1 9 Chip Select 2 9 Chip Select 3 9 Chip Select Registers 68 Chip Select x Bus Mode Control Register 71 Chip Select x Control Register 70 Chip Select x Lower Bound Register 68 Chip Select x Upper Bound Register 69 Chip Select/Wait State Generator block 5, 6, 7, 8, 9 Chip Selects and Wait States 49 Chip Selects During Bus Request/Bus Acknowledge Cycles 53 Clear to Send 13, 16, 119, 122 clock divisor value, 16-bit 110, 135 clock initialization circuitry 186 Clock Peripheral Power-Down Registers 37 clock phase bit 131-133, 137 clock polarity bit 132-133, 137 Clock Synchronization 143 Clocking Overview 140 Complex triggers 186 CONTINUOUS mode 77, 79-83, 85-86 CPHA--see clock phase bit CPOL--see clock polarity bit
B
Baud Rate Generator 109 Control Registers 110 Functional Description 134 BCD--see binary-coded-decimal operation binary-coded-decimal operation 88, 90-103 bit generation 104 Block Diagram 2 Boundary-Scan Architecture 186 break detection 104, 113 break point trigger functions 186 Bus Acknowledge 11, 22, 53, 168, 178, 184, 237 pin 53, 178 Bus Arbitration Overview 140
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CPU system clock cycle 55 CS0 9, 21, 49-52 CS1 9, 21, 49-52 CS2 9, 21, 49, 51-52 CS3 9, 21, 49, 51-52 CTS--see Clear to Send CTS0 13, 128 CTS1 16 Customer Feedback Form 253 cycle termination signal 65
DTACK--see cycle termination signal DTR--see Data Terminal Ready DTR0 14, 128 DTR1 16
E
edge-selectable interrupts 44 edge-triggered interrupt input 128 edge-triggered interrupt mode 42, 44 Edge-Triggered Interrupts 43 EI, Op Code Map 211 Electrical Characteristics 221 Enabling and Disabling the WDT 74 ENAB--see Bus Enable bit endec--see Infrared Encoder/Decoder 38, 124- 125, 128-129 Erase operations 192-193 Event Counter 81 External Bus Acknowledge Timing 237 external bus request 53, 164, 168 External I/O Chip Selects 24 External I/O Read Timing 232 External I/O Write Timing 233 External Memory Read Timing 229 External Memory Write Timing 230 external pull-down resistor 41 External System Clock Driver (PHI) Timing 237 eZ80 Bus Mode 54, 67, 71 eZ80 CPU 10, 36, 53, 57, 58, 65, 170, 186 Core 32 Instruction Set 207 eZ80 Product ID Low and High Byte Registers 181 eZ80 Product ID Revision Register 182 eZ80(R) system clock cycle 54-55, 58, 61 EZ80F92 3, 73, 170, 182 EZ80F92 processor 1-2, 4-5, 9, 24, 36, 40, 46, 47- 49, 51, 67, 77, 81, 108-109, 152, 162-164, 166, 174-175, 179, 180, 184, 218, 221, 223, 228, 237
D
data bus 9, 53-54, 56-58, 61, 65, 71, 90, 168, 178, 184 Data Carrier Detect 14, 16, 119, 122 Delta Change Status Of 122 Data Set Ready 14, 16, 119, 122 Delta Change Status Of 122 Data Terminal Ready 14, 16, 119, 122 Delta Change Status Of 122 Data Transfer Procedure with SPI configured as a Slave 135 Data Transfer Procedure with SPI Configured as the Master 134 data transfer, SPI 138 Data Validity 141 DC Characteristics 221 DCD--see Data Carrier Detect DCD0 14, 128 DCD1 16 DCTS 122 DDCD--see Data Carrier Detect, Delta Change Status Of DDSR--see Data Set Ready, Delta Change Status Of DDTR--see Data Terminal Ready, Delta Change Status Of divisor count 110, 135 Document Information 242 Document Number Description 242 DSR--see Data Set Ready DSR0 14, 128 DSR1 16
F
FAST mode 140, 160 Features, eZ80 CPU Core 32
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Flash Memory 190, 192 Arrangement in the eZ80F93 193 Overview 193 framing error 104, 106, 113 full-duplex transmission 133 Functional Description, Infrared Encoder/Decoder 124
G
General-Purpose Input/Output 40 Control Registers 44 Interrupts 43 modes 41-42 Operation 40 Overview 40 Port Input Sample Timing 236 Port Output Timing 238 port pins 33, 40, 45 GND--see Ground GPIO--see General-Purpose Input/Output Ground 2
H
HALT instruction 36, 174, 182, 209 HALT mode 1, 11, 36-37, 222, 223, 227 HALT, Op-Code Map 211 HALT_SLP 11 handshake 104, 145 high-frequency system clock 134
I
I/O Chip Select Operation 24, 51 I/O space 5-10, 49, 51 I2C--see Inter-Integrated Circuit IEEE Standard 1149.1 186-187 IEF--see Interrupt Enable Flag IEF1 47-48, 183 IEF2 47-48 IFLG bit 140, 145, 148, 150-151, 155, 157-158 IM 0, Op Code Map 214 IM 1, Op Code Map 214
IM 2, Op Code Map 214 Information Page 192-193, 196, 201, 203-205 Infrared Data Association 124 Encoder/Decoder--see Infrared Encoder/Decoder specifications 124 standard 124 standard baud rates 124 transceiver 128 Transmit Data 12 Infrared Encoder/Decoder 12, 38, 124, 128 Register 129 Signal Pins 128 Input/Output Request 10-11, 21, 52, 54-55, 57-58, 61 Assertion Delay 232-233 Deassertion Delay 232-233 Hold Time 234 INSTRD--see instruction read indicator Instruction Read Indicator 11, 21 Instruction Store 4 0 Registers 179 Intel Bus Mode (Multiplexed Address and Data Bus) 61 Intel Bus Mode (Separate Address and Data Buses) 57 Inter-Integrated Circuit Acknowledge bit 142, 146-148, 150-151, 155 bus 140, 144, 152 bus clock 140 bus protocol 141 Clock Control Register 159 Control Register 154 Data Register 154 Extended Slave Address Register 153 General Characteristics 140 Registers 152 Serial Clock 19, 23, 140-142, 159 Serial Data 19, 23, 140-142, 144, 151 Serial I/O Interface 140 Slave Address Register 152 Software Reset Register 160 Status Register 157 internal pull-up 41
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internal system clock 52 Interrupt Controller 46 Interrupt Enable bit 11, 89, 107, 154 Interrupt Enable Flag 48, 183 interrupt input 12-16, 18-19 interrupt request 42-44, 46-48, 83, 202 interrupt service routine 46, 48 SPI 46 interrupt vector 46-47 address 47-48 interrupt, highest-priority 46-47 interrupts, edge-selectable 44 Introduction to On-Chip Instrumentation 186 Introduction, ZiLOG Debug Interface 161 IORQ--see Input/Output Request IR_RxD modulation signal 13, 125-129 IR_TxD modulation signal 12, 125, 128, 129 IrDA--see Infrared Data Association IRQ 47 IRQ_EN 83, 134, 137 IRQ_EN bit 80 ISR--see interrupt service routine IVECT 46, 47, 48
level-sensitive interrupt modes 42 level-sensitive interrupts 44 Level-triggered Interrupts 43 line break detection 104 Loopback Testing, Infrared Encoder/Decoder 128 low-byte vector 46 Low-Power Modes 36 lsb--see least-significant bit LSB--see least-significant byte
M
maskable interrupt 37 sources 46 vectors 47 Maskable Interrupts 46 Mass Erase operation 196, 201-202, 204-206 Mass Erase Violation 202 Master In, Slave Out 19, 131, 133 MASTER mode 132, 140, 155, 157-160 MASTER mode 150-151, 156 Start bit 145-147, 149-150, 152, 155-156, 158 Stop bit 146-147, 149-150, 152, 155-156, 158 MASTER mode, SPI 133 Master Out, Slave In 19, 131, 133 Master Receive 140, 148 MASTER TRANSMIT mode 140, 145 MASTER_EN bit 133 Memory and I/O Chip Selects 49 Memory Chip Select Example 50 Memory Chip Select Operation 49 Memory Chip Select Priority 50 Memory Request 10-11, 21, 49, 54-55, 57-58, 61, 230-231 Hold Time 231 memory space 49, 51 Memory Write 196 MISO--see Master In, Slave Out mode fault 133, 138 Mode Fault error flag 131, 133, 138 Modem status signal 13-14, 16 MODF--see Mode Fault error flag MOSI--see Master Out, Slave In most-significant bit 85-86,105-106, 131, 142, 154,
J
Jitter, Infrared Encoder/Decoder 128 JTAG--see Joint Test Action Group Joint Test Action Group interface 186 Mode Select Input 12, 22, 187, 238 mode selection 187 Test Clock 12, 22, 162, 186-187, 238 Test Data In 12, 22, 162, 187, 238 Test Data Out 12 Test Mode 12 Test Trigger Output 12
L
least-significant bit 84-85, 105, 145-146, 148, 151, 157, 163 least-significant byte 47-48, 85, 159, 175 level-sensitive interrupt input 128
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EZ80F92/eZ80F93 Product Specification
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157, 163, 166, 203 most-significant byte 86 Motorola Bus Mode 64 Motorola-compatible 54 MREQ--see Memory Request msb--see most significant bit MSB--see most-significant byte Multibyte I/O Write (Row Programming) 195 multimaster conflict 133, 138
overrun error 104, 106, 113, 121 Overview, Low-Power Modes 36
P
Packaging 239 Page Erase operation 196, 202-203, 205-206 Page Erase Violation 202 Part Number Description 240 PB1 81 PHI 19, 23 Pin Characteristics 20 Pin Description 4 POP, Op Code Map 211, 213, 215 POR--see Power-On Reset Port x Alternate Register 1 45 Port x Alternate Register 2 45 Port x Data Direction Registers 45 Port x Data Registers 44 Power connections 2 Power-On Reset 33, 223 and VBO Electrical Characteristics 223 Voltage Threshold 223 voltage threshold 33, 34 Precharacterization Product 241 Program Counter 36-37, 47-48 Programmable Reload Timer Operation 78 Programmable Reload Timer Registers 82 Programmable Reload Timers 77 Programmable Reload Timers Overview 77 Programming Flash Memory 194 pull-up resistor, external 41, 140 PUSH, Op Code Map 211, 213, 215
N
NACK--see Not Acknowledge NMI 11, 22, 32, 37, 46, 48, 73-75 NMI_flag bit 75 NMI_OUT bit 75 nonmaskable interrupt 11, 32, 37, 47-48, 73-75 Return from 210 Not Acknowledge 142, 146-150, 155, 158
O
OCI--see On-Chip Instrumentation On-Chip Instrumentation 186 Activation 186 clock pin 186 Information Requests 188 Interface 187 Introduction to 186 pins 187 On-Chip Oscillators 218 On-chip pull-up 187 Op Code maps 211 Open source I/O 41 Open-drain I/O 41 open-drain mode 41 Open-drain output 41 open-drain output 140 open-source mode 41 open-source output 12-19, 41 Operating Modes 145 Operation of the EZ80F92 Device During ZDI Breakpoints 167 Ordering Information 240
R
RAM--see Random Access Memory Random Access Memory 189 Address Upper Byte Register 191 Control Register 191 Static 1, 161, 198, 240 RD--see Read instruction Read instruction 10, 21, 49, 52, 54, 57-58, 61 Assertion Delay 230, 232
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Deassertion Delay 230, 232 Reading the Current Count Value 80 Real-Time Clock 12, 24, 29, 33, 36, 77, 88, 218, 219 alarm 36, 89 alarm condition 102 Alarm Control Register 102 Alarm Day-of-the-Week Register 101 Alarm Hours Register 100 Alarm Minutes Register 99 alarm registers 89 Alarm Seconds Register 98 Battery Backup 89 Century Register 97 circuit 222 clock source 102 Control Register 102 count 89, 102 count registers 90 Crystal Input 11 Crystal Output 12 Day-of-the-Month Register 94 Day-of-the-Week Register 93 Hours Register 92 Minutes Register 91 Month Register 95 Oscillator and Source Selection 89 Overview 88 Power Supply 12 Recommended Operation 89 Registers 90 Seconds Register 90 source 73, 75, 77, 81, 87 Supply Current 222 Supply Voltage 222 Year Register 96 Receive, Infrared Encoder/Decoder 125 Recommended Usage of the Baud Rate Generator 109 Register Map 24 Request to Send 13, 15, 119, 122, 128 RESET 11, 21, 33-34, 36-37, 41, 49, 73-75, 89- 90, 102, 109-111, 129, 134, 135, 172, 174, 186- 187, 189, 191, 199, 201, 223
Reset 33 controller 33-34 event 40 mode timer 33 Operation 33 Or NMI Generation 74 States 50 Resetting the I2C Registers 152 RI--see Ring Indicator RI0 14, 128 RI1 17, 42 Ring Indicator 14, 17, 106, 119, 122 Trailing Edge of 122 Row Program Time-out 202 RST_FLAG bit 74 RTC--see Real-Time Clock RTC_UNLOCK 103 RTC_UNLOCK bit 89, 90, 102 RTC_VDD 12, 22 RTC_XIN 11, 22 RTC_XOUT 12, 22 RTS--see Request to Send RTS0 13 RTS1 15 RxD0 13 RxD1 15
S
Schmitt Trigger Input 11, 20 SCK--see SPI Serial Clock SCL--see I2C Serial Clock SCL line 143-145 SCLK--see system clock SDA--see I2C serial data serial bus, SPI 139 Serial Clock 131, 140 Serial Clock, I2C 19 Serial Clock, SPI 18, 131 Serial Data 131, 140 Serial Data, I2C 19 Serial Peripheral Interface 38, 46, 130-131, 133 Baud Rate Generator 134 Baud Rate Generator Register 27
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Baud Rate Generator Registers--Low Byte and High Byte 135 Block 27 Control Register 27, 137 Data Rate 134 Flags 133, 138-139 Functional Description 133 interrupt service routine 46 master device 19, 135 MASTER mode 133 mode 18 Receive Buffer Register 27, 139 Registers 135 serial bus 139 Signals 131 slave device 19 SLAVE mode 133 status bit 139 Status Register 27, 134, 138 Transmit Shift Register 27, 134-135, 139 Setting Timer Duration 78 Shift Left Arithmetic 147, 149, 153, 210 Op Code Map 212, 216-217 Shift Right Arithmetic 210 Op Code Map 212, 216 SINGLE PASS mode 77-80, 82 Single-Byte I/O Write Operations 194 SLA--see Shift Left Arithmetic SLAVE mode 140, 151-153, 155, 158 SLAVE mode, SPI 133 Slave Receive 140, 151 Slave Select Slave Select 18, 131-134, 138 slave transmit mode 140, 150 SLEEP mode 11, 36, 102, 174, 182, 222, 223, 228 sleep-mode recovery 102 sleep-mode recovery reset 24 Software break point instruction 186 SPI--see Serial Peripheral Interface SPI Serial Clock 18, 131 Idle State 132 pin 133, 137 Receive Edge 132 signal 133 Transmit Edge 132
SPIF--see Serial Peripheral Interface Flags SRA--see Shift Right Arithmetic SRAM--see Random Access Memory, Static SS--see Slave Select STA--see MASTER mode start bit standard mode 140 START and STOP Conditions 141 START bit 163 START condition 141, 143-144, 147-149, 151- 152, 155-160 Start Condition, ZDI 163 Starting Program Counter 47, 48 STOP condition 141-142, 144-145, 148, 150-151, 155-156, 158-160 STP--see MASTER mode stop bit supply voltage 2, 33-34, 41, 140, 221-223 Switching Between Bus Modes 67 System Clock 19, 33, 36-39, 42-43, 73, 75, 77, 81, 109, 134, 159-160, 167 system clock cycle, CPU 54-55, 58, 61 system clock cycles 11, 52-54, 58, 62, 66, 74, 186 system clock delay 67 System Clock Frequency 78, 81, 86, 161-162 System Clock Oscillator Input 17 System Clock Oscillator Output 17 system clock period 187 system clock rising edge 86, 109, 134 system clock, high-frequency 134 system clock, internal 52 System Reset 11, 33
T
T0_IN 17 T1_IN 18 T4_OUT 18 T5_OUT 19 TCK--see JTAG Test Clock TDI--see JTAG Test Data In TDO--see JTAG Test Data Out 12, 22, 187, 238 TERI--see Ring Indicator, Trailing Edge of Test Access Port 186 Test Mode 187 Time-Out Period Selection 74
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Timer 0 In 17 Timer 1 In 18 Timer Control Register 82 Timer Data Register--High Byte 84 Timer Data Register--Low Byte 84 Timer Input Source Select Register 86 Timer Input Source Selection 81 Timer Interrupts 80 Timer Output 81 Timer Reload Register--High Byte 86 TMS--see JTAG Mode Select Input Trace buffer memory 186 Trace history buffer 186 Transferring Data 142 transmit shift register 105, 113, 117, 120, 133 Transmit Shift Register, SPI 134-135, 139 Transmit, Infrared Encoder/Decoder 125 TRIGOUT 12, 22, 187 TxD0 12 TxD1 15
Registers 111 Scratch Pad Register 123 Transmit Holding Register 111 Transmitter 105 Transmitter Interrupt 107
V
VBO--see Voltage Brown-Out VCC--see supply voltage Voltage Brown-Out 33, 223 protection circuitry 34 Reset 34 Voltage Threshold 33-34, 223 voltage, supply 2, 33, 34-41, 140, 221-222 VVBO--see Voltage Brown-Out threshold
W
WAIT condition 1, 11, 21, 58, 61, 65, 205 WAIT Input Signal 52 WAIT pin, external 54, 55 WAIT Request 11 WAIT state 55, 62, 234-235 Timing for Read Operations 234 Timing for Write Operations 235 WAIT states 47, 52-55, 61, 70, 168, 189, 199, 223- 225 Wait States 49, 52, 199, 222 Watch-Dog Timer 33, 36, 73-75,167 clock sources 73-75 Control Register 24, 75 Operation 74 Overview 73 Registers 75 RESET 24, 75 Reset Register 76 time-out 37, 73-76 time-out period 74, 76 time-out reset 24 time-out values 74 WCOL--see Write Collision WDT--see Watch-Dog Timer WR--see Write instruction
U
UART--see Universal Asynchronous Receiver/ Transmitter Universal Asynchronous Receiver/Transmitter Baud Rate Generator Register --Low and High Bytes 110 FIFO Control Register 115 Functional Description 105 Functions 105 Interrupt Enable Register 113 Interrupt Identification Register 114 Interrupts 106 Line Control Register 116 Line Status Register 120 Modem Control 106 Modem Control Register 119 Modem Status Interrupt 107 Modem Status Register 121 Receive Buffer Register 112 Receiver 106 Receiver Interrupts 107 Recommended Usage 108
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Write Collision 133-134, 138 SPI 138 Write instruction 10-11, 21, 49, 52, 55, 58, 61, 231, 234 Write Violation 202
X
XIN 17, 23 XOUT 17, 23
Z
Z80 Bus Mode 54 Z80 Memory mode 180, 184 ZCL--see ZiLOG Debug Interface Clock ZDA--see ZiLOG Debug Interface Data ZDI_BUS_STAT 168, 170, 184 ZDI_BUSACK_EN 168, 184 ZDI--see ZiLOG Debug Interface 161-162, 186 ZDI-Supported Protocol 162 ZiLOG Debug Interface 161, 186 Address Match Registers 170 Block Read 167 BLOCK WRITE 166 Break 173 BREAK Control Register 171 BREAK mode 183 Bus Control Register 178 Bus Status Register 184
Clock 162-163, 165, 172 Clock and Data Conventions 162 Clock Frequency 162 Clock pin 162 Data 162-163, 172, 187 Data pin 162 data transfer 164 debug control 186 Debug mode 164, 178, 184 master 164, 166-167, 179-180, 184 Master Control Register 174 Read Memory Register 184 Read Operations 166 Read Register Low, High, and Upper 183 Read/Write Control Register 175 Read-Only Registers 170 Register Addressing 164 Register Definitions 170 Single-Bit Byte Separator 164 Single-Byte Read 166 SINGLE-BYTE WRITE 165 slave 163, 166, 167 START command 164 Start Condition 163 START signal 163 Status Register 182 Write Data Registers 175 Write Memory Register 180 Write Operations 165 Write-Only Registers 169
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The EZ80F92/eZ80F93 Product Specification
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